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    CONSTRAINED NANOSECOND LASER ANNEAL OF METAL INTERCONNECT STRUCTURES
    2.
    发明申请
    CONSTRAINED NANOSECOND LASER ANNEAL OF METAL INTERCONNECT STRUCTURES 有权
    金属互连结构的约束纳米激光雷达

    公开(公告)号：US20160086849A1

    公开(公告)日：2016-03-24

    申请号：US14490792

    申请日：2014-09-19

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    发明人： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

    摘要： In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

    摘要翻译： 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

    INTEGRATED CIRCUITS WITH STRESSED SEMICONDUCTOR SUBSTRATES AND PROCESSES FOR PREPARING INTEGRATED CIRCUITS INCLUDING THE STRESSED SEMICONDUCTOR SUBSTRATES
    4.
    发明申请
    INTEGRATED CIRCUITS WITH STRESSED SEMICONDUCTOR SUBSTRATES AND PROCESSES FOR PREPARING INTEGRATED CIRCUITS INCLUDING THE STRESSED SEMICONDUCTOR SUBSTRATES 审中-公开
    具有应力半导体衬底的集成电路和用于制备集成电路的工艺，包括应力半导体衬底

    公开(公告)号：US20150287824A1

    公开(公告)日：2015-10-08

    申请号：US14244322

    申请日：2014-04-03

    申请人： GLOBALFOUNDRIES, Inc.

    发明人： Shishir Ray ,  Jin Ping Liu ,  Bharat Krishnan

    IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L21/268 ,  H01L21/265 ,  H01L29/167

    CPC分类号： H01L21/268 ,  H01L21/26513 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78 ,  H01L29/7847

    摘要： Integrated circuits with stressed semiconductor substrates, processes for preparing stressed semiconductor substrates, and processes for preparing integrated circuits including stressed semiconductor substrates are provided herein. An exemplary process for preparing a stressed semiconductor substrate includes providing a semiconductor substrate of a semiconductor material having a first crystalline lattice constant; introducing a dopant on and into a surface layer of the semiconductor substrate via ion implantation at an amount above a solubility limit of the dopant in the semiconductor material to form a dopant-containing surface layer of the semiconductor substrate; applying energy to the dopant-containing surface layer of the semiconductor substrate with an ultra-short pulse laser to form a molten semiconductor:dopant layer on a surface of the semiconductor substrate; and removing the energy such that the molten semiconductor:dopant layer forms a solid semiconductor:dopant layer with a second crystalline lattice having a second lattice constant that differs from the first lattice constant.

    摘要翻译： 具有应力半导体衬底的集成电路，制备受压半导体衬底的工艺，以及制备包括应力半导体衬底的集成电路的工艺。 制备应力半导体衬底的示例性方法包括提供具有第一晶格常数的半导体材料的半导体衬底; 在半导体材料中以高于掺杂剂的溶解度极限的量经由离子注入在半导体衬底的表面层上引入掺杂剂，以形成半导体衬底的掺杂剂表面层; 用超短脉冲激光对半导体衬底的掺杂剂表面层施加能量，以在半导体衬底的表面上形成熔融半导体：掺杂剂层; 并且去除能量，使得熔融半导体：掺杂剂层形成固体半导体：具有与第一晶格常数不同的第二晶格常数的第二晶格的掺杂剂层。

    Method of fabricating an interlayer structure of increased elasticity modulus
    5.
    发明授权
    Method of fabricating an interlayer structure of increased elasticity modulus 有权
    制造弹性模量增加的层间结构的方法

    公开(公告)号：US09076645B1

    公开(公告)日：2015-07-07

    申请号：US14272554

    申请日：2014-05-08

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Shishir Ray ,  Sandeep Gaan ,  Jin Ping Liu ,  Zhiguo Sun

    IPC分类号： H01L21/31 ,  H01L21/02

    CPC分类号： H01L21/02112 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02255 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/7682 ,  H01L21/76828 ,  H01L2221/1047

    摘要： Circuit structure fabrication methods are provided which include: providing an interlayer structure above a substrate, the interlayer structure including porogens dispersed within a dielectric material; and pulse laser annealing the interlayer structure to form a treated interlayer structure, the pulse laser annealing polymerizing the dielectric material of the interlayer structure to form a polymeric dielectric material, that includes pores disposed therein. The pulse laser annealing facilitates increasing elasticity modulus of the treated interlayer structure by, in part, maintaining structural integrity of the treated interlayer structure, notwithstanding that there are pores disposed within the polymeric dielectric material which, for instance, facilitates reducing dielectric constant of the treated interlayer structure.

    摘要翻译： 提供了电路结构制造方法，其包括：在基底之上提供层间结构，所述层间结构包括分散在电介质材料内的致孔剂; 并且脉冲激光退火层间结构以形成经处理的层间结构，脉冲激光退火聚合层间结构的电介质材料以形成聚合物电介质材料，其包括设置在其中的孔。 脉冲激光退火有助于通过部分地维持经处理的层间结构的结构完整性来提高经处理的层间结构的弹性模量，尽管在聚合物电介质材料内设置孔，其例如有助于降低经处理的层间结构的介电常数 夹层结构。

    Fabricating transistors having resurfaced source/drain regions with stressed portions
    7.
    发明授权
    Fabricating transistors having resurfaced source/drain regions with stressed portions 有权
    制造具有应力部分的具有重新覆盖的源极/漏极区域的晶体管

    公开(公告)号：US09559166B2

    公开(公告)日：2017-01-31

    申请号：US14609504

    申请日：2015-01-30

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Shishir Ray ,  Bharat Krishnan ,  Min-hwa Chi

    IPC分类号： H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L29/04 ,  H01L21/268

    CPC分类号： H01L29/0847 ,  H01L21/268 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7847 ,  H01L29/7848

    摘要： Methods are providing for fabricating transistors having at least one source region or drain region with a stressed portion. The methods include: forming, within a cavity of a substrate structure, the at least one source region or drain region with the internal stress; and resurfacing the at least one source region or drain region to reduce surface defects of the at least one source region or drain region without relaxing the stressed portion thereof. For instance, the resurfacing can include melting an upper portion of the at least one source region or drain region. In addition, the resurfacing can include re-crystallizing an upper portion of the at least one source region or drain region, and/or providing the at least one source region or drain region with at least one {111} surface.

    摘要翻译： 提供制造具有至少一个具有应力部分的源极区或漏极区的晶体管的方法。 所述方法包括：在衬底结构的空腔内形成具有内部应力的至少一个源极区域或漏极区域; 以及重新铺展所述至少一个源极区域或漏极区域以减少所述至少一个源极区域或漏极区域的表面缺陷，而不放松其应力部分。 例如，表面重排可以包括熔化至少一个源区或漏区的上部。 另外，重新表面可以包括重新结晶至少一个源区或漏区的上部，和/或向至少一个源区或漏区提供至少一个{111}表面。

    Semiconductor substrates and methods for processing semiconductor substrates
    9.
    发明授权
    Semiconductor substrates and methods for processing semiconductor substrates 有权
    半导体衬底和半导体衬底的处理方法

    公开(公告)号：US09570291B2

    公开(公告)日：2017-02-14

    申请号：US14798796

    申请日：2015-07-14

    申请人： GLOBALFOUNDRIES, Inc.

    发明人： Shishir Ray ,  Sandeep Gaan ,  Sheldon Meyers ,  Nisha Pillai ,  Edmund Kenneth Banghart ,  Kyle Jung

    IPC分类号： G03F7/26 ,  H01L21/02 ,  H01L29/16

    CPC分类号： H01L29/1604 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/31058

    摘要： Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

    摘要翻译： 提供半导体衬底和半导体衬底的处理方法。 一种用于处理半导体衬底的方法包括提供在外边缘和中心区域之间具有外边缘，中心区域和周边区域的半导体衬底。 半导体衬底也具有上表面。 该方法包括在周边区域的半导体衬底的上表面上形成无定形材料。 此外，该方法包括照射半导体衬底的上表面，其中非晶态材料抑制在半导体衬底的外边缘处的裂纹。

    SEMICONDUCTOR SUBSTRATES AND METHODS FOR PROCESSING SEMICONDUCTOR SUBSTRATES
    10.
    发明申请
    SEMICONDUCTOR SUBSTRATES AND METHODS FOR PROCESSING SEMICONDUCTOR SUBSTRATES 有权
    半导体衬底和半导体衬底的处理方法

    公开(公告)号：US20170018426A1

    公开(公告)日：2017-01-19

    申请号：US14798796

    申请日：2015-07-14

    申请人： GLOBALFOUNDRIES, Inc.

    发明人： Shishir Ray ,  Sandeep Gaan ,  Sheldon Meyers ,  Nisha Pillai ,  Edmund Kenneth Banghart ,  Kyle Jung

    IPC分类号： H01L21/02 ,  H01L29/16

    CPC分类号： H01L29/1604 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/31058

    摘要： Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

    摘要翻译： 提供半导体基板和用于制造集成电路的方法。 一种用于制造集成电路的方法包括提供在外边缘和中心区域之间具有外边缘，中心区域和周边区域的半导体基板。 半导体衬底也具有上表面。 该方法包括在周边区域的半导体衬底的上表面上形成无定形材料。 此外，该方法包括照射半导体衬底的上表面，其中非晶态材料抑制在半导体衬底的外边缘处的裂纹。