公开(公告)号：US20190067115A1

公开(公告)日：2019-02-28

申请号：US15683968

申请日：2017-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro PARK ,  Laertis ECONOMIKOS ,  Ruilong XIE ,  Min Gyu SUNG

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/768 ,  H01L29/66

Abstract: A method of manufacturing a FinFET structure involves forming a gate cut within a sacrificial gate layer and backfilling the gate cut opening with an etch selective dielectric later. Lateral etching of the dielectric layer after removing remaining portions of the sacrificial gate can be used to increase the distance between the gate cut (isolation) structure and an adjacent fin relative to methods that do not perform a step of trimming the dielectric layer.

公开(公告)号：US20200083363A1

公开(公告)日：2020-03-12

申请号：US16126775

申请日：2018-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Laertis ECONOMIKOS ,  Jiehui SHU ,  Ruilong XIE

IPC: H01L29/78 ,  H01L29/66 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.

公开(公告)号：US20180233579A1

公开(公告)日：2018-08-16

申请号：US15430647

申请日：2017-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui-feng LI ,  Laertis ECONOMIKOS

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/762 ,  H01L29/66795

Abstract: A method for forming gate cuts during RMG processing and the resulting device are provided. Embodiments include forming Si fins over a substrate; forming a STI layer over the substrate and recessed, exposing upper portions of the Si fins; forming polysilicon dummy gate electrodes perpendicular to the Si fins, separated by STI regions, on the upper portions of the Si fins and on the STI layer between the Si fins; forming a hardmask over the polysilicon dummy gate electrodes; etching through the hardmask and polysilicon dummy gate electrodes forming cavities between some of the Si fins; oxidizing polysilicon exposed on sides of the cavities and any residual polysilicon remaining at a bottom of one or more of the cavities; filling the cavities with SiN; removing the polysilicon dummy gate electrodes; and forming RMGs.

公开(公告)号：US20200091143A1

公开(公告)日：2020-03-19

申请号：US16134173

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Ruilong XIE ,  Laertis ECONOMIKOS

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.

公开(公告)号：US20200035543A1

公开(公告)日：2020-01-30

申请号：US16047078

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Haiting WANG ,  Hong YU ,  Laertis ECONOMIKOS

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A methodology for forming a fin field effect transistor (FinFET) includes the co-integration of various isolation structures, including gate cut and shallow diffusion break isolation structures that are formed with common masking and etching steps. Following an additional patterning step to provide segmentation for source/drain conductive contacts, a single deposition step is used to form an isolation dielectric layer within each of gate cut openings, shallow diffusion break openings and cavities over shallow trench isolation between device active areas.