中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.014 seconds)

    THRESHOLD VOLTAGE ADJUSTMENT IN A FIN TRANSISTOR BY CORNER IMPLANTATION
    3.
    发明申请
    THRESHOLD VOLTAGE ADJUSTMENT IN A FIN TRANSISTOR BY CORNER IMPLANTATION 有权
    通过角膜植入在晶状体中进行阈值电压调整

    公开(公告)号：US20140027825A1

    公开(公告)日：2014-01-30

    申请号：US14039450

    申请日：2013-09-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    IPC: H01L29/78

    CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886

    Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

    Abstract translation: 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

    Threshold voltage adjustment in a fin transistor by corner implantation
    4.
    发明授权
    Threshold voltage adjustment in a fin transistor by corner implantation 有权
    通过角落植入对鳍式晶体管进行阈值电压调节

    公开(公告)号：US08916928B2

    公开(公告)日：2014-12-23

    申请号：US14039450

    申请日：2013-09-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

    CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886

    Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

    Abstract translation: 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

    Method of forming a semiconductor structure including a vertical nanowire
    5.
    发明授权
    Method of forming a semiconductor structure including a vertical nanowire 有权
    形成包括垂直纳米线的半导体结构的方法

    公开(公告)号：US08835255B2

    公开(公告)日：2014-09-16

    申请号：US13747907

    申请日：2013-01-23

    Applicant: Globalfoundries Inc.

    Inventor： Tim Baldauf ,  Stefan Flachowsky ,  Tom Hermann ,  Ralf Illgen

    IPC: H01L21/336

    CPC classification number: H01L29/66666 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/775

    Abstract: A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.

    Abstract translation: 一种方法包括提供包括衬底和衬底上方的纳米线的半导体结构。 纳米线包括第一半导体材料并沿着衬底的垂直方向延伸。 在衬底上形成材料层。 材料层环绕着纳米线。 相对于材料层选择性地去除纳米线的第一部分。 纳米线的第二部分不会被删除。 远离衬底的纳米线的第二部分的远端比材料层的表面更靠近衬底，使得半导体结构在纳米线的位置具有凹陷。 纳米线的远端暴露在凹槽的底部。 凹部填充有第二半导体材料。 第二半导体材料与第一半导体材料不同地掺杂。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A VERTICAL NANOWIRE
    6.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A VERTICAL NANOWIRE 有权
    形成包括垂直纳米线的半导体结构的方法

    公开(公告)号：US20140206157A1

    公开(公告)日：2014-07-24

    申请号：US13747907

    申请日：2013-01-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Tim Baldauf ,  Stefan Flachowsky ,  Tom Herrmann ,  Ralf Illgen

    IPC: H01L29/66

    CPC classification number: H01L29/66666 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/775

    Abstract: A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.

    Abstract translation: 一种方法包括提供包括衬底和衬底上方的纳米线的半导体结构。 纳米线包括第一半导体材料并沿着衬底的垂直方向延伸。 在衬底上形成材料层。 材料层环绕着纳米线。 相对于材料层选择性地去除纳米线的第一部分。 纳米线的第二部分不会被删除。 远离衬底的纳米线的第二部分的远端比材料层的表面更靠近衬底，使得半导体结构在纳米线的位置具有凹陷。 纳米线的远端暴露在凹槽的底部。 凹部填充有第二半导体材料。 第二半导体材料与第一半导体材料不同地掺杂。

Patent Agency Ranking