公开(公告)号：US10176859B2

公开(公告)日：2019-01-08

申请号：US15585709

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Duenkel ,  Ralf Illgen ,  Ralf Richter ,  Soeren Jansen

IPC: G11C16/24 ,  G11C11/22 ,  H01L29/78 ,  G11C16/04 ,  G11C16/06

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

公开(公告)号：US09899417B2

公开(公告)日：2018-02-20

申请号：US15467305

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L27/12 ,  H01L21/265 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.

公开(公告)号：US20150214121A1

公开(公告)日：2015-07-30

申请号：US14677503

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ralf Illgen ,  Stefan Flachowsky

IPC: H01L21/84 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L21/3213 ,  H01L29/161 ,  H01L29/78 ,  H01L29/167 ,  H01L21/28 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/16

CPC classification number: H01L21/84 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02636 ,  H01L21/28035 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1203 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78696

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body fully depleted silicon-on-insulator substrate. The method forms a temporary gate structure over the substrate and forms lightly doped source/drain extension areas around the gate structure. Further, the method includes performing an annealing process on the lightly doped source/drain extension areas. Outdiffusion from the lightly doped source/drain extensions is less than 5 nm during the annealing process. The method includes forming a strain region around the gate structure.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供绝缘体上绝缘体上的绝缘体上的超薄体。 该方法在衬底上形成临时栅极结构，并在栅极结构周围形成轻掺杂的源极/漏极延伸区域。 此外，该方法包括对轻掺杂源极/漏极延伸区域进行退火处理。 在退火过程中，轻掺杂源极/漏极扩展部分的扩散不足5nm。 该方法包括在栅极结构周围形成应变区域。

公开(公告)号：US20140361335A1

公开(公告)日：2014-12-11

申请号：US13914288

申请日：2013-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Gerd Zschaezsch

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

Abstract: A device includes a substrate, a P-channel transistor and an N-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second semiconductor material. The first and second semiconductor materials have different crystal lattice constants. The P-channel transistor includes a channel region having a compressive stress in a first portion of the substrate. The channel region of the P-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. The N-channel transistor includes a channel region having a tensile stress formed in a second portion of the substrate. The channel region of the N-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. Methods of forming the device are also disclosed.

Abstract translation: 一种器件包括衬底，P沟道晶体管和N沟道晶体管。 衬底包括第一半导体材料的第一层和第二半导体材料的第二层。 第一和第二半导体材料具有不同的晶格常数。 P沟道晶体管包括在衬底的第一部分中具有压应力的沟道区。 P沟道晶体管的沟道区域包括第一半导体材料的第一层的一部分和第二半导体材料的第二层的一部分。 N沟道晶体管包括在衬底的第二部分中形成的具有拉伸应力的沟道区。 N沟道晶体管的沟道区域包括第一半导体材料的第一层的一部分和第二半导体材料的第二层的一部分。 还公开了形成装置的方法。

公开(公告)号：US20180322912A1

公开(公告)日：2018-11-08

申请号：US15585709

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Duenkel ,  Ralf Illgen ,  Ralf Richter ,  Soeren Jansen

IPC: G11C11/22 ,  H01L29/78 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C11/225 ,  G11C16/0466 ,  G11C16/06 ,  H01L29/78391 ,  H01L29/7841

Abstract: The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material.

公开(公告)号：US09685457B2

公开(公告)日：2017-06-20

申请号：US14805827

申请日：2015-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/265 ,  H01L21/84 ,  H01L21/324

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed. The formation of the first transistor includes forming a dummy gate structure over the layer of semiconductor material, forming a source region of the first transistor and a drain region of the first transistor in portions of the semiconductor substrate adjacent the dummy gate structure, forming an electrically insulating structure annularly enclosing the dummy gate structure and performing a replacement gate process. The replacement gate process includes removing the dummy gate structure and a portion of the layer of semiconductor material below the dummy gate structure, wherein a recess is formed in the electrically insulating structure. The recess is filled with an electrically conductive material.

公开(公告)号：US20140117418A1

公开(公告)日：2014-05-01

申请号：US13663941

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Three-dimensional transistors may be formed on the basis of high mobility semiconductor materials, which may be provided locally restricted in the channel region by selective epitaxial growth processes without using a mask material for laterally confining the growing of the high mobility semiconductor material. That is, by controlling process parameters of the selective epitaxial growth process, the cross-sectional shape may be adjusted without requiring a mask material, thereby reducing overall process complexity and providing an additional degree of freedom for adjusting the transistor characteristics in terms of threshold voltage, drive current and electrostatic control of the channel region.

Abstract translation: 可以基于高迁移率半导体材料形成三维晶体管，高迁移率半导体材料可以通过选择性外延生长工艺局部限制在沟道区域中，而不用掩模材料横向地限制高迁移率半导体材料的生长。 也就是说，通过控制选择性外延生长工艺的工艺参数，可以调节横截面形状而不需要掩模材料，从而降低总体工艺复杂性，并提供用于根据阈值电压调整晶体管特性的附加自由度 ，驱动通道区域的电流和静电控制。

公开(公告)号：US10056376B2

公开(公告)日：2018-08-21

申请号：US15238023

申请日：2016-08-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823462 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/512 ,  H01L29/516 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.

公开(公告)号：US20180040731A1

公开(公告)日：2018-02-08

申请号：US15231105

申请日：2016-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/786 ,  H01L21/324 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/7849 ,  H01L21/02181 ,  H01L21/02356 ,  H01L21/28291 ,  H01L21/324 ,  H01L21/76251 ,  H01L21/76254 ,  H01L29/66742 ,  H01L29/786 ,  H01L29/78654

Abstract: A semiconductor-on-insulator wafer includes a support substrate, an electrically insulating layer over the support substrate and a semiconductor layer over the electrically insulating layer. A semiconductor structure includes a transistor. The transistor includes an electrically insulating layer including a piezoelectric material over a support substrate, a semiconductor layer over the electrically insulating layer, a source region, a channel region and a drain region in the semiconductor layer, a gate structure over the channel region, a first electrode and a second electrode. The first electrode and the second electrode are provided at laterally opposite sides of the electrically insulating layer. The first and second electrodes are electrically insulated from the semiconductor layer and configured for applying a voltage to the piezoelectric material of the electrically insulating layer. The piezoelectric material creates a strain at least in the channel region in response to the voltage applied thereto.

公开(公告)号：US09583240B2

公开(公告)日：2017-02-28

申请号：US14469012

申请日：2014-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01C7/10 ,  H01C1/16 ,  H01C7/02 ,  H01C7/04 ,  H01C7/00 ,  H01C17/075

CPC classification number: H01C1/16 ,  H01C7/008 ,  H01C7/021 ,  H01C7/027 ,  H01C7/041 ,  H01C17/075

Abstract: The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.

Abstract translation: 本公开内容涉及包括正温度系数热敏电阻和负温度系数热敏电阻的半导体结构，该正温度系数热敏电阻和负温度系数热敏电阻通过连接元件彼此并联连接，连接元件被构造成使得由并联连接产生的电阻在预定的 温度范围和相应的制造方法。