公开(公告)号：US09142674B2

公开(公告)日：2015-09-22

申请号：US14176767

申请日：2014-02-10

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanxiang Liu ,  Michael Hargrove ,  Christian Gruensfelder

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7851

Abstract: Fin field-effect transistor devices and methods of forming the fin field-effect transistor devices are provided herein. In an embodiment, a fin field-effect transistor device includes a semiconductor substrate that has a fin. A gate electrode structure overlies the fin. Source and drain halo and/or extension regions and epitaxially-grown source regions and drain regions are formed in the fin and are disposed adjacent to the gate electrode structure. A body contact is disposed on a contact surface of the fin, and the body contact is spaced separately from the halo and/or extension regions and the epitaxially-grown source regions and drain regions.

Abstract translation: 翅片场效应晶体管器件和形成鳍式场效应晶体管器件的方法在本文中提供。 在一个实施例中，鳍状场效应晶体管器件包括具有鳍片的半导体衬底。 栅极电极结构覆盖翅片。 源极和漏极卤素和/或延伸区域和外延生长的源极区域和漏极区域形成在鳍状物中并且邻近栅电极结构设置。 体接触件设置在翅片的接触表面上，并且体接触件与卤素和/或延伸区域和外延生长的源极区域和漏极区域分开地间隔开。

公开(公告)号：US09087860B1

公开(公告)日：2015-07-21

申请号：US14264179

申请日：2014-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Edmund Kenneth Banghart ,  Yanxiang Liu ,  Shesh Mani Pandey

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/085 ,  H01L21/76 ,  H01L29/06 ,  H01L29/167 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L29/66803 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0638 ,  H01L29/1083 ,  H01L29/167

Abstract: Methods are provided for fabricating a fin-type field effect transistor(s), having a channel region within a fin. The methods include: establishing a protective material above an upper surface of the fin, and an isolation material adjacent to at least one sidewall of the fin, the isolation material being recessed down from the upper surface of the fin, for instance, for approximately a height of the channel region within the fin; and providing a punch-through stop dopant region within the fin below the channel region, the providing including implanting a punch-through stop dopant into the isolation material and laterally diffusing the punch-through stop dopant from the isolation material into the fin to form the punch-through stop region within the fin beneath the channel region.

Abstract translation: 提供了用于制造翅片式场效应晶体管的方法，其具有鳍内的沟道区。 所述方法包括：在翅片的上表面上方建立保护材料，以及邻近翅片的至少一个侧壁的隔离材料，隔离材料从翅片的上表面向下凹下，例如约 翅片内的通道区域的高度; 以及在通道区域下方的翅片内提供穿通止动掺杂剂区域，所述提供包括将穿通阻止掺杂剂注入到隔离材料中并将穿通阻止掺杂剂横向扩散到隔离材料进入翅片以形成 在通道区域下方的翅片内的穿通停止区域。

公开(公告)号：US09064868B2

公开(公告)日：2015-06-23

申请号：US13650233

申请日：2012-10-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Vara Vakada ,  Jerome Ciavatti

IPC: H01L29/66 ,  H01L23/522

CPC classification number: H01L23/5225 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.

Abstract translation: 本文公开的一种说明性器件包括晶体管，其包括形成在半导体衬底中的栅电极和漏区，形成在衬底中的隔离结构，其中隔离结构横向地位于栅电极和漏区之间，法拉第屏蔽 其位于栅极电极和漏极区域之间并且隔离结构之上，其中法拉第屏蔽具有相对于衬底的上表面基本垂直取向的长轴。

公开(公告)号：US20150016174A1

公开(公告)日：2015-01-15

申请号：US13937962

申请日：2013-07-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L27/112 ,  G11C17/16 ,  H01L21/768

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L21/76816 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus are provided for an integrated circuit with a programmable electrical connection. The apparatus includes an inactive area with a memory line passing over the inactive area. The memory line includes a programmable layer. An interlayer dielectric is positioned over the memory line and the inactive area, and an extending member extends through the interlayer dielectric. The extending member is electrically connected to the programmable layer of the memory line at a point above the inactive area.

Abstract translation: 为具有可编程电气连接的集成电路提供了方法和装置。 该装置包括具有通过非活动区域的存储器线路的无效区域。 存储线包括可编程层。 层间电介质位于存储器线路和无源区域之上，并且延伸部件延伸穿过层间电介质。 延伸构件在非活动区域上方的点处电连接到存储器线路的可编程层。

公开(公告)号：US08846476B2

公开(公告)日：2014-09-30

申请号：US13766922

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Manfred Eller ,  Johannes van Meer

IPC: H01L21/8236 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418

Abstract: One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.

Abstract translation: 本文公开的一种说明性方法涉及形成由分别形成在第一和第二活性区域中和第二活性区域上的第一和第二N型晶体管组成的集成电路产品。 该方法通常涉及对第一和第二有源区域执行公共阈值电压调整离子注入过程，形成第一和第二晶体管，执行非晶离子注入工艺，以在第一有源区域中选择性地形成非晶材料区域，但不在第 第二有源区，在执行非晶化离子注入工艺之后，在第一和第二晶体管上方形成覆盖材料层，并执行重结晶退火工艺，以将非晶材料区域的至少一部分转化为结晶材料。 在一些情况下，封盖材料层可以由杨氏模量为至少180GPa的材料形成。

公开(公告)号：US20140120708A1

公开(公告)日：2014-05-01

申请号：US13664744

申请日：2012-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US09577040B2

公开(公告)日：2017-02-21

申请号：US15189079

申请日：2016-06-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Jianwei Peng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Francis Benistant

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/268 ,  H01L29/10 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L21/324 ,  H01L29/165

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract translation: 公开了一种形成具有突然，垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在半导体鳍片上方并垂直于半导体鳍片形成栅电极; 在栅电极的相对侧上形成第一间隔物; 在所述翅片的相对侧上形成第二间隔物; 在第二间隔件之间形成邻近第一间隔件的翅片中的空腔; 在每个腔中部分地外延生长源/漏区; 将第一掺杂剂注入部分生长的源极/漏极区域中，其后可选择的RTA; 在空腔中外延生长源/漏区的剩余部分，原位掺杂有第二掺杂剂; 以及在源极/漏极区域中注入第三掺杂剂。

公开(公告)号：US09437740B2

公开(公告)日：2016-09-06

申请号：US14686228

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

公开(公告)号：US09252272B2

公开(公告)日：2016-02-02

申请号：US14083164

申请日：2013-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.

Abstract translation: 这里在一个实施例中阐述了具有从体硅衬底延伸的翅片的FinFET半导体器件，其中形成为围绕鳍的一部分围绕栅极缠绕，并且其中靠近与栅极对准的鳍的沟道区域 形成与栅极对准的局部掩埋氧化物区域。 在一个实施例中，局部掩埋氧化物区域形成在鳍片的沟道区域的下方。

公开(公告)号：US20140361365A1

公开(公告)日：2014-12-11

申请号：US13912448

申请日：2013-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu

IPC: H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: One illustrative device includes a source region and a drain region formed in a substrate, wherein the source/drain regions are doped with a first type of dopant material, a gate structure positioned above the substrate that is laterally positioned between the source region and the drain region and a drain-side well region positioned in the substrate under a portion, but not all, of the entire lateral width of the drain region, wherein the drain-side well region is also doped with the first type of dopant material. The device also includes a source-side well region positioned in the substrate under an entire width of the source region and under a portion, but not all, of the drain region and a part of the extension portion of the drain region is positioned under a portion of the gate structure.

Abstract translation: 一个说明性器件包括形成在衬底中的源极区域和漏极区域，其中源极/漏极区域掺杂有第一类型的掺杂剂材料，位于衬底上方的栅极结构，该栅极结构横向地位于源极区域和漏极 区域和位于衬底中的漏极侧阱区域，其位于漏极区域的整个横向宽度的部分但不是全部，其中漏极侧阱区域还掺杂有第一类型的掺杂剂材料。 该器件还包括源极侧阱区域，其位于源极区域的整个宽度的整个宽度之下且在漏极区域的一部分但不是全部的位置处，并且漏极区域的延伸部分的一部分位于 部分门结构。