公开(公告)号：US20160049495A1

公开(公告)日：2016-02-18

申请号：US14461887

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kristina TREVINO ,  Yuan-Hung LIU ,  Gabriel Padron WELLS ,  Xing ZHANG ,  Hoong Shing WONG ,  Chang Ho MAENG ,  Taejoon HAN ,  Gowri KAMARTHY ,  Isabelle ORAIN ,  Ganesh UPADHYAYA

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/3213 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/517

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Abstract translation: 提供半导体结构和制造方法，其包括例如在半导体衬底上提供栅极结构，所述栅极结构包括多个共形栅极层和设置在多个共形栅极层内的栅极材料; 将多个共形栅极层的一部分凹陷在栅极结构的上表面之下，其中凹入的多个共形栅极层的上表面是共面的; 以及去除所述栅极材料的一部分以便于所述栅极材料的剩余部分的上表面与所述凹入的多个共形栅极层的上表面共面。

公开(公告)号：US20150132962A1

公开(公告)日：2015-05-14

申请号：US14076386

申请日：2013-11-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang HU ,  Dae-Han CHOI ,  Dae Geun YANG ,  Taejoon HAN ,  Andy WEI

IPC: H01L21/308

CPC classification number: H01L21/0337

Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

Abstract translation: 通过以下方式促进掩模图案形成：提供掩模结构，其包括设置在基板结构上方的至少一个牺牲间隔结构; 将掩模层保形地设置在掩模结构上; 选择性地去除间隔层，至少部分地留下沿着至少一个牺牲间隔结构的侧壁的侧壁间隔物，并且在衬底结构上方提供至少一个额外的牺牲间隔物，该至少一个额外的牺牲隔离物 间隔件与所述至少一个牺牲间隔结构设置成间隔开的关系; 以及去除所述至少一个牺牲间隔结构，将所述侧壁间隔物和所述至少一个另外的牺牲隔离物留在所述衬底结构上作为掩模图案的一部分。

公开(公告)号：US20150076111A1

公开(公告)日：2015-03-19

申请号：US14031563

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang HU ,  Gabriel PADRON WELLS ,  Jack Chao-Hsu CHANG ,  Mingmei WANG ,  Taejoon HAN

IPC: H01J37/32

CPC classification number: H01J37/32146 ,  H01J37/32174 ,  H01J2237/3341 ,  H01J2237/3348 ,  H01L21/3065 ,  H01L21/32137

Abstract: Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic.

Abstract translation: 通过改变对蚀刻系统的射频（RF）功率脉冲的供应，便于蚀刻系统蚀刻结构的特征。 变化通过至少一个特征提供所提供的RF功率脉冲中提供的RF功率脉冲的至少一个RF功率脉冲，其偏离所提供的RF功率脉冲的一个或多个其它RF功率脉冲。