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    SENSOR AND METHOD OF FORMING THE SAME
    2.
    发明申请
    SENSOR AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220271177A1

    公开(公告)日：2022-08-25

    申请号：US17741467

    申请日：2022-05-11

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Lanxiang WANG ,  Shyue Seng TAN ,  Eng Huat TOH

    IPC: H01L31/02 ,  H01L31/028 ,  H01L31/18 ,  H01L31/0392 ,  H01L31/107 ,  H01L31/0312

    Abstract: A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.

    RRAM DEVICES AND METHODS OF FORMING RRAM DEVICES
    3.
    发明申请
    RRAM DEVICES AND METHODS OF FORMING RRAM DEVICES 有权

    公开(公告)号：US20210313512A1

    公开(公告)日：2021-10-07

    申请号：US16840471

    申请日：2020-04-06

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Xinshu CAI ,  Shyue Seng TAN ,  Eng Huat TOH

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A resistive random access memory (RRAM) device may be provided, including: a base layer, a vertical electrode stack arranged over the base layer, where the vertical electrode stack may include alternating mask elements and first electrodes, and each first electrode may include an extended portion extending beyond at least one side surface of at least one mask element adjoining the first electrode, a switching layer arranged along the extended portion of each first electrode and along the at least one side surface of the at least one mask element adjoining the first electrode, and a second electrode including a surface in contact with the switching layer. The RRAM device may have a 3D structure.

    DEVICES WITH LOWER RESISTANCE AND IMPROVED BREAKDOWN AND METHOD FOR PRODUCING THE SAME
    4.
    发明申请
    DEVICES WITH LOWER RESISTANCE AND IMPROVED BREAKDOWN AND METHOD FOR PRODUCING THE SAME 审中-公开

    公开(公告)号：US20200381521A1

    公开(公告)日：2020-12-03

    申请号：US16995397

    申请日：2020-08-17

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Shyue Seng TAN ,  Elgin Kiok Boone QUEK

    IPC: H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

    Abstract: Methods of forming a ferroelectric material layer below a field plate for achieving increased Vbr with reduced Rdson and resulting devices are provided. Embodiments include forming a N-Drift in a portion of the Si layer formed in a portion of a p-sub; forming an oxide layer over portions of the Si layer and the N-Drift; forming a gate over a portion of the oxide layer; forming a S/D extension region in the Si layer; forming first and second spacers on opposite sides of the gate and the oxide layer; forming a S/D region in the Si layer adjacent to the S/D extension region and a S/D region in the N-Drift remote from the Si layer; forming a U-shaped ferroelectric material layer over the oxide layer and the N-Drift, proximate or adjacent to the gate; and filling the U-shaped ferroelectric material layer with a metal, a field gate formed.

    HIGH COUPLING RATIO SPLIT GATE MEMORY CELL
    5.
    发明申请
    HIGH COUPLING RATIO SPLIT GATE MEMORY CELL 审中-公开

    公开(公告)号：US20190057970A1

    公开(公告)日：2019-02-21

    申请号：US15681442

    申请日：2017-08-21

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Yuan SUN ,  Shyue Seng TAN ,  Eng Huat TOH

    IPC: H01L27/1156 ,  H01L27/11558 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L29/423

    Abstract: A split gate non-volatile memory (NVM) cell formed on a crystalline-on-insulator (COI) substrate, such as a fully or partially depleted silicon-on-insulator (SOI) substrate is disclosed. The split gate memory cell includes a split gate disposed on a surface substrate of the SOI substrate between source/drain (S/D) regions. The split gate includes a storage gate with a control gate (CG) over a floating gate (FG), and a select gate (SG). A back gate is provided on the bulk substrate below a buried oxide (BOX). The back gate may be doped with the same polarity type dopants as the S/D regions. The back gate is coupled to the CG to increase CG coupling ratio, improving programming performance. Alternatively, the back gate may be doped with the opposite polarity type dopants as the S/D regions. The back gate is coupled to a negative bias during program and erase operations. The negative bias increases the gate threshold voltages of the SG and CG, resulting in higher electron generation efficiency to improve programming speed as well as a higher electric field to increase erase speed.

    VERTICAL RANDOM ACCESS MEMORY WITH SELECTORS
    6.
    发明申请
    VERTICAL RANDOM ACCESS MEMORY WITH SELECTORS 审中-公开

    公开(公告)号：US20160293665A1

    公开(公告)日：2016-10-06

    申请号：US15182625

    申请日：2016-06-15

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Yuan SUN ,  Elgin Kiok Boone QUEK ,  Shyue Seng TAN ,  Xuan Anh TRAN

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2445 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16

    Abstract: Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure. The selector element includes respective first and second selector diodes for the first and second memory elements of each of the one or more cell stacks.

    COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY
    9.
    发明申请
    COMPACT LOCALIZED RRAM CELL STRUCTURE REALIZED BY SPACER TECHNOLOGY 有权
    紧凑的本地化RRAM细胞结构由间隔技术实现

    公开(公告)号：US20150188047A1

    公开(公告)日：2015-07-02

    申请号：US14633508

    申请日：2015-02-27

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Shyue Seng TAN ,  Eng Huat TOH ,  Elgin QUEK

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1675 ,  H01L45/1691

    Abstract: An RRAM is disclosed with a vertical BJT selector. Embodiments include defining a STI region in a substrate, implanting dopants in the substrate to form a first polarity well around and below a bottom portion of the STI region, a second polarity channel over the well on opposite sides of the STI region, and a first polarity active area over each channel at the surface of the substrate, forming an RRAM liner on the active area and STI region, forming a sacrificial top electrode on the RRAM liner, forming spacers on opposite sides of the sacrificial top electrode, implanting a second polarity dopant in the active area on opposite sides of the sacrificial top electrode, forming a silicon oxide adjacent the spacers, removing at least a portion of the sacrificial top electrode forming a cavity, forming in the cavity inner spacers adjacent the spacers and a top electrode.

    Abstract translation: 公开了一种具有垂直BJT选择器的RRAM。 实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域的底部周围和下方形成第一极性，在STI区域的相对侧上的阱上的第二极性沟道，以及第一 在衬底的表面上的每个通道上的极性有源区域，在有源区域和STI区域上形成RRAM衬垫，在RRAM衬垫上形成牺牲顶部电极，在牺牲顶部电极的相对侧上形成间隔物，注入第二极性 在牺牲顶部电极的相对侧上的有源区域中形成掺杂剂，在间隔物附近形成氧化硅，去除形成空腔的牺牲顶部电极的至少一部分，在空腔中形成邻近间隔物的内部间隔物和顶部电极。

    SIMPLE AND COST-FREE MTP STRUCTURE
    10.
    发明申请
    SIMPLE AND COST-FREE MTP STRUCTURE 有权
    简单和免费的MTP结构

    公开(公告)号：US20150001608A1

    公开(公告)日：2015-01-01

    申请号：US14253878

    申请日：2014-04-16

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Shyue Seng TAN ,  Eng Huat TOH ,  Jeoung Mo KOO ,  Danny SHUM ,  Elgin Kiok Boone QUEK

    IPC: H01L29/788

    CPC classification number: H01L29/42324 ,  G11C16/0425 ,  H01L27/11558 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

    Abstract: Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. A non-volatile MTP memory cell includes a substrate, first and second wells disposed in the substrate, a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well and sharing a diffusion region. The memory cell further includes a control gate disposed over the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and the second wells.

    Abstract translation: 提出了一种用于非易失性存储单元的简单且无成本的多时间可编程（MTP）结构的实施例。 非易失性MTP存储单元包括衬底，设置在衬底中的第一和第二阱，具有选择栅极的第一晶体管和具有彼此相邻并且布置在第二阱上并且共享扩散区域的浮置栅极的第二晶体管。 存储单元还包括设置在第一阱上的控制栅极。 控制栅极耦合到浮动栅极，并且控制和浮置栅极包括延伸穿过第一和第二阱的相同栅极层。

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