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    FIN SELECTOR WITH GATED RRAM
    1.
    发明申请
    FIN SELECTOR WITH GATED RRAM 审中-公开

    公开(公告)号：US20180033963A1

    公开(公告)日：2018-02-01

    申请号：US15729314

    申请日：2017-10-10

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Elgin QUEK ,  Shyue Seng TAN

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.

    FINFET
    3.
    发明申请
    FINFET 有权

    公开(公告)号：US20150069512A1

    公开(公告)日：2015-03-12

    申请号：US14542676

    申请日：2014-11-17

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Jae Gon LEE ,  Chung Foong TAN ,  Elgin QUEK

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/786

    CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/78603

    Abstract: A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduce height variations across the wafer. The fin type transistor may also include a counter doped region at least below the S/D regions to reduce parasitic capacitance to improve its performance.

    Abstract translation: 翅片型晶体管包括在衬底表面上的用于将晶体管的栅极与衬底隔离的介质层。 电介质层包括非选择性蚀刻的表面，以产生翅片结构的顶部，其具有减小横跨晶片的高度变化。 翅片型晶体管还可以包括至少低于S / D区的反掺杂区域，以减小寄生电容以改善其性能。

    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE
    5.
    发明申请
    LDMOS WITH IMPROVED BREAKDOWN VOLTAGE 审中-公开
    LDMOS具有改进的断电电压

    公开(公告)号：US20150325697A1

    公开(公告)日：2015-11-12

    申请号：US14713819

    申请日：2015-05-15

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Jae Gon LEE ,  Chung Foong TAN ,  Elgin QUEK

    IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

    Abstract: An LDMOS is formed with a second gate stack over n− drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.

    Abstract translation: LDMOS由n-漂移区上的第二栅极堆叠形成，具有与栅极堆叠相同的公共栅电极，并具有比栅叠层更高的功函数。 实施例包括：包括基板的装置; 在衬底中的第一阱和第二阱，所述第一阱掺杂有第一导电类型的掺杂剂，所述第二阱掺杂有第二导电型掺杂剂，所述第二阱围绕所述第一阱; 第一口井的源头和第二口井的排水沟; 所述第一阱中的所述第一导电类型掺杂剂的掺杂区域，所述掺杂区域用作与所述第一阱的体接触; 在第一井的一部分上的第一栅极堆叠; 在第二阱的一部分上的第二栅极堆叠，第一和第二栅极堆叠具有公共栅电极。

    SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE
    6.
    发明申请
    SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE 审中-公开
    分屏门闪存显示减少干扰

    公开(公告)号：US20150255471A1

    公开(公告)日：2015-09-10

    申请号：US14716951

    申请日：2015-05-20

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Shyue Seng TAN ,  Elgin QUEK

    IPC: H01L27/115 ,  H01L29/51

    CPC classification number: H01L27/11517 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/513

    Abstract: A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

    Abstract translation: 分离栅极存储单元由在栅极和存储器栅极堆叠之间的包含高k材料的介电隔离器制造。 实施例包括具有包含低k和高k层的电介质间隔物的存储单元。 其他实施例包括在字门和存储器栅叠层之间具有气隙的存储单元。

    NOVEL COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY
    10.
    发明申请
    NOVEL COMPACT CHARGE TRAP MULTI-TIME PROGRAMMABLE MEMORY 审中-公开
    新颖的紧凑充电捕获多时间可编程存储器

    公开(公告)号：US20150236034A1

    公开(公告)日：2015-08-20

    申请号：US14704004

    申请日：2015-05-05

    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

    Inventor： Eng Huat TOH ,  Khee Yong LIM ,  Shyue Seng TAN ,  Elgin QUEK

    IPC: H01L27/115 ,  H01L29/51 ,  H01L29/792 ,  H01L29/49

    CPC classification number: H01L27/11568 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    Abstract: A memory device requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: a substrate; a gate stack on the substrate; a source and drain in the substrate at opposite sides, respectively, of the gate stack; a source extension region in the substrate adjacent the source region, wherein no drain extension region is formed on the other side of the gate stack; a tunnel oxide liner on the substrate at each side of the gate stack and on side surfaces of the gate stack; and a charge-trapping (CT) spacer on each tunnel oxide liner.

    Abstract translation: 公开了一种不需要或最小的附加掩模的存储器件，其具有低成本，小占地面积和多次编程能力。 实施例包括：基板; 衬底上的栅极堆叠; 分别在栅叠层的相对侧的衬底中的源极和漏极; 邻近所述源极区域的所述衬底中的源极延伸区域，其中在所述栅极叠层的另一侧上不形成漏极延伸区域; 栅极堆叠的每一侧的基板上以及栅极堆叠的侧表面上的隧道氧化物衬垫; 和每个隧道氧化物衬垫上的电荷捕获（CT）间隔物。

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