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    COST-EFFECTIVE METHOD TO FORM A RELIABLE MEMORY DEVICE WITH SELECTIVE SILICIDATION AND RESULTING DEVICE
    2.
    发明申请
    COST-EFFECTIVE METHOD TO FORM A RELIABLE MEMORY DEVICE WITH SELECTIVE SILICIDATION AND RESULTING DEVICE 审中-公开

    公开(公告)号：US20190148395A1

    公开(公告)日：2019-05-16

    申请号：US16247159

    申请日：2019-01-14

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Soh Yun Siah

    IPC分类号： H01L27/11568 ,  H01L21/3205 ,  H01L21/02 ,  H01L27/11521

    摘要： A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.

    SHIELDED MRAM CELL
    5.
    发明申请
    SHIELDED MRAM CELL 审中-公开

    公开(公告)号：US20190221732A1

    公开(公告)日：2019-07-18

    申请号：US15874077

    申请日：2018-01-18

    申请人： GLOBALFOUNDRIES Singapore Pte Ltd

    发明人： Dimitri Houssameddine ,  Chenchen Jacob Wang ,  Bin Liu ,  Soh Yun Siah

    IPC分类号： H01L43/02 ,  H01L23/552 ,  H01L27/22

    摘要： One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

    Integrated two-terminal device with logic device for embedded application
    9.
    发明授权
    Integrated two-terminal device with logic device for embedded application 有权

    公开(公告)号：US10446607B2

    公开(公告)日：2019-10-15

    申请号：US15393200

    申请日：2016-12-28

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Wanbing Yi ,  Curtis Chun-I Hsieh ,  Juan Boon Tan ,  Soh Yun Siah ,  Hai Cong ,  Alex See ,  Young Seon You ,  Danny Pak-Chum Shum ,  Hyunwoo Yang

    IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12

    摘要： Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the dual damascene interconnect in the second region is coupled to the two-terminal device element.