公开(公告)号：US20240347638A1

公开(公告)日：2024-10-17

申请号：US18301382

申请日：2023-04-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette ,  James P. Mazza ,  Hong Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28123 ,  H01L29/1037 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.

公开(公告)号：US20250086657A1

公开(公告)日：2025-03-13

申请号：US18463668

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter T. Coutu ,  Romain H.A. Feuillette ,  Alain F. Loiseau

IPC: G06Q30/018 ,  G06K7/14

Abstract: A system and computerized method verify product custody along a product manufacturing chain. The method may include verifying a first machine-readable (MR) code for a product level N is valid by comparing the first MR code to a database of valid MR codes. Where the first MR code for the product level N is verified as valid, a second, valid MR code is generated for a next product level N+1 in the database of valid MR codes. In addition, the first MR code for the product level N in the database of valid MR codes is invalidated, so it cannot be used again. The second MR code is formed for use with the next product level N+1, e.g., by the downstream product manufacturer. Custody of product levels along a manufacturing chain can be verified and secured, avoiding bad actors from inserting and profiting from fake parts into the manufacturing chain.

公开(公告)号：US20250031439A1

公开(公告)日：2025-01-23

申请号：US18354114

申请日：2023-07-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234

Abstract: A disclosed structure includes a semiconductor fin on a substrate and an isolation region on the substrate laterally surrounding a lower portion of the fin. A fin-type field effect transistor (FINFET) includes an upper portion of the fin and an isolation structure, and a gate structure are on the isolation region and positioned laterally adjacent to the upper portion of the fin. The gate structure also extends over the top of the fin and abuts the isolation structure. The FINFET also includes an independently biasable supplementary gate structure integrated into the isolation structure. Specifically, an opening extends into the isolation structure adjacent to, but separated from, the fin. The supplementary gate structure includes a conductor layer within the opening and that portion of the isolation structure between the conductor layer and the semiconductor fin. Also disclosed are associated methods.

公开(公告)号：US20250006650A1

公开(公告)日：2025-01-02

申请号：US18341893

申请日：2023-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alain F. Loiseau ,  Romain H.A. Feuillette ,  Mujahid Muhammad ,  Peter T. Coutu

IPC: H01L23/544 ,  G01R31/28

Abstract: An integrated circuit (IC) includes a plurality of metal layers, and a machine-readable code in a selected metal layer of the plurality of metal layers. A wafer includes a plurality of the ICs. An IC wafer testing system includes a scanner configured to read the machine-readable code in the metal layer of the IC in the wafer, and a tester configured to perform testing on the IC in the wafer based on testing information obtained from storage based on the machine-readable code. A method may include forming the IC including a plurality of metal layers and forming a selected metal layer of the IC including the machine-readable code in metal in the selected metal layer. The method may further include testing the IC. The machine-readable code reduces the complexity and time needed to setup and test an IC in a wafer.

公开(公告)号：US20250148181A1

公开(公告)日：2025-05-08

申请号：US18503212

申请日：2023-11-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bradley A. Orner ,  Romain H.A. Feuillette ,  Vivienne A.B. Miller ,  Petar Ivanov Todorov ,  Stephen T. Burgess

IPC: G06F30/3308 ,  G02B27/00

Abstract: Disclosed are a photonic integrated circuit (PIC) design system and method including optical signal propagation simulation with coupling awareness to account for transition loss due to a difference between at least one specific physical parameter (e.g., curvature radius, material composition, etc.) in optically coupled photonic devices. Coupling awareness can be achieved by including, within a bus of a netlist between the photonic devices, at least one pair of physical data pins: one associated with a specific physical parameter in the light emitting photonic device and the other associated with the specific physical parameter in the light receiving photonic device. Alternatively, coupling awareness can be achieved by running a utility to identify a parameter mismatch between the light emitting and receiving photonic devices, developing a custom coupling cell to account for the mismatch, and inserting the custom coupling cell into a design layout for the PIC.

公开(公告)号：US20240028811A1

公开(公告)日：2024-01-25

申请号：US17813344

申请日：2022-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alain F. Loiseau ,  Romain H.A. Feuillette ,  Mujahid Muhammad

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A process design kit (PDK) is supplied to a layout design tool. The PDK includes parameterized cells (Pcells) adapted to cause the layout design tool to automatically add labels to device layouts in the graphic design system (GDS) file that is being created by the layout design tool. Each corresponding label lists parameters used when creating the corresponding device layout. The GDS file is receive back from the layout design tool. The parameters from the labels is applied to corresponding ones of the Pcells within the PDK to create a device verification layout for each of the device layouts in the GDS file. Each of the device layouts in the GDS file is compared to a corresponding device verification layout. The device layouts within the GDS file that fail to match the corresponding device verification layout are thereby identified.

公开(公告)号：US20220268805A1

公开(公告)日：2022-08-25

申请号：US17183432

申请日：2021-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Romain H.A. Feuillette ,  David C. Pritchard ,  Elizabeth Strehlow ,  James P. Mazza

IPC: G01P15/00

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.