公开(公告)号：US20160307826A1

公开(公告)日：2016-10-20

申请号：US15197861

申请日：2016-06-30

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL ,  Greg P. KLOWAK ,  Ahmad MIZAN ,  Stephen COATES

IPC: H01L23/495 ,  H01L29/78 ,  H01L23/31 ,  H01L29/20

CPC classification number: H01L23/3114 ,  H01L21/4828 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L29/2003 ,  H01L29/7816 ,  H01L2224/0239 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/352 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40227 ,  H01L2224/40245 ,  H01L2224/40475 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/73203 ,  H01L2224/73263 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/84815 ,  H01L2224/8484 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/04642 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/81 ,  H01L2224/48

Abstract: Packaging solutions for devices and systems comprising lateral GaN power transistors are disclosed, including components of a packaging assembly, a semiconductor device structure, and a method of fabrication thereof. In the packaging assembly, a GaN die, comprising one or more lateral GaN power transistors, is sandwiched between first and second leadframe layers, and interconnected using low inductance interconnections, without wirebonding. For thermal dissipation, the dual leadframe package assembly can be configured for either front-side or back-side cooling. Preferred embodiments facilitate alignment and registration of high current/low inductance interconnects for lateral GaN devices, in which contact areas or pads for source, drain and gate contacts are provided on the front-side of the GaN die. By eliminating wirebonding, and using low inductance interconnections with high electrical and thermal conductivity, PQFN technology can be adapted for packaging GaN die comprising one or more lateral GaN power transistors.

Abstract translation: 公开了包括横向GaN功率晶体管的器件和系统的封装解决方案，包括封装组件的部件，半导体器件结构及其制造方法。 在封装组件中，包括一个或多个横向GaN功率晶体管的GaN管芯被夹在第一和第二引线框层之间，并且使用低电感互连互连，而无需引线接合。 为了散热，双引线框封装组件可以配置为正面或背面冷却。 优选的实施例有利于用于横向GaN器件的高电流/低电感互连的对准和配准，其中用于源极，漏极和栅极接触的接触区域或焊盘设置在GaN管芯的前侧。 通过消除引线键合，并且使用具有高导电和导热性的低电感互连，PQFN技术可以适用于封装包含一个或多个横向GaN功率晶体管的GaN晶体管。

公开(公告)号：US20240213110A1

公开(公告)日：2024-06-27

申请号：US18085660

申请日：2022-12-21

Applicant: GaN Systems Inc.

Inventor： An-Sheng CHENG ,  Stephen COATES

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/3192 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/32 ,  H01L29/401 ,  H01L29/41775 ,  H01L2224/32225 ,  H01L2924/1033 ,  H01L2924/13064

Abstract: Embedded die packaging for semiconductor power switching devices, wherein the package comprises a laminated body comprising a layer stack of a plurality of dielectric layers and conductive metal layers. A thermal contact area on a back-side of the die is attached to a leadframe. A patterned layer of conductive metallization on a front-side of the die provides electrical contact areas of the power semiconductor device. Before embedding, a protective dielectric layer is provided on the front-side of the die, extending around edges of the die. The protective dielectric layer provides a protective region that acts a cushion to protect edges of the die from damage during lamination. The protective dielectric material may extend over the electrical contact areas to protect against etch damage and damage during laser drilling of vias, thereby mitigating physical damage, overheating or other potential damage to the active region of the semiconductor device.