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公开(公告)号：US09389275B2
公开(公告)日：2016-07-12
申请号：US13362208
申请日：2012-01-31
IPC分类号： G01R35/00 , G01R31/319
CPC分类号： G01R31/3191
摘要： Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.
摘要翻译： 与测量操作一起提供测量系统校准的技术。 这些技术可以包括在测量系统内的信号处理链中提供参考装置。 激励信号可以通过参考装置驱动，同时其可以连接到测量系统内的信号处理链，并且可以捕获校准响应。 在测量操作期间，参考设备连接可以与信号处理链中的传感器连接互补，激励信号可以通过信号处理链驱动。 可以从系统捕获测量响应。 测量系统可以产生校准的测量信号，其根据校准响应和测量响应考虑系统内的相位和/或幅度误差。
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公开(公告)号：US20130193982A1
公开(公告)日：2013-08-01
申请号：US13362208
申请日：2012-01-31
IPC分类号： G01R35/00
CPC分类号： G01R31/3191
摘要： Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.
摘要翻译： 与测量操作一起提供测量系统校准的技术。 这些技术可以包括在测量系统内的信号处理链中提供参考装置。 激励信号可以通过参考装置驱动，同时其可以连接到测量系统内的信号处理链，并且可以捕获校准响应。 在测量操作期间，参考设备连接可以与信号处理链中的传感器连接互补，激励信号可以通过信号处理链驱动。 可以从系统捕获测量响应。 测量系统可以产生校准的测量信号，其根据校准响应和测量响应考虑系统内的相位和/或幅度误差。
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公开(公告)号：US20060213270A1
公开(公告)日：2006-09-28
申请号：US11370764
申请日：2006-03-08
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
IPC分类号： G01P15/125
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.
摘要翻译： 用于感测电容器的电容的单端电容器接口电路包括具有输入共模电压的差分积分放大器和电压基本上等于输入共模电压的两个求和节点，用于将电容器充电到第一 电压电平在第一阶段中，在第二阶段将电容器连接到差分放大器的求和节点之一，以提供基本上代表第一电压电平和输入共模电压之间的差的第一输出变化，以及 也代表电容器; 在第三相中将电容器充电到第二电压电平，并且在第四相中将电容器连接到差分放大器的另一个求和节点，以提供基本上代表第二电压电平与第二电压电平之间的差的第二输出变化 输入共模电压，也代表电容; 组合的第一和第二输出变化表示电容器的电容基本上独立于输入共模电压。
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公开(公告)号：US07304483B2
公开(公告)日：2007-12-04
申请号：US11821746
申请日：2007-06-25
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.
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公开(公告)号：US20070247171A1
公开(公告)日：2007-10-25
申请号：US11821746
申请日：2007-06-25
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
IPC分类号： G01R27/26
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.
摘要翻译： 用于感测第一和第二电容器的电容的差分电容器一端电容器接口电路包括具有第一和第二求和节点和输入共模电压的差分积分放大器; 以及切换电路，用于将所述差分一端电容器的第一电容器充电到所述差分一端电容器的第一电容器和所述差分一端电容器的第二电容器到第一相位的第二电压电平，所述第二相位将所述第一电容器连接到所述 第一求和节点和所述第二电容器到所述放大器的所述第二求和节点，以在第三阶段提供基本上代表所述第一和第二电压电平与所述输入共模电压之间的差的第一和第二输出变化， 所述第二电压电平和所述第二电容器达到所述第一电压电平，并且在将所述第一电容器与所述第二求和节点和所述第二电容器连接到所述放大器的所述第一求和节点的第四阶段中，以提供基本上代表 所述第一和第二电压电平与所述输入共模之间的差 电压，组合的第一，第二，第三和第四变化表示所述第一和第二电容器的电容基本上独立于所述输入共模电压。
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公开(公告)号：US07235983B2
公开(公告)日：2007-06-26
申请号：US11370764
申请日：2006-03-08
申请人： John O'Dowd , Damien McCartney , Gabriel Banarie
发明人： John O'Dowd , Damien McCartney , Gabriel Banarie
CPC分类号： G01D5/24 , G01P15/125 , H03M3/34 , H03M3/458
摘要： A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.
摘要翻译： 用于感测电容器的电容的单端电容器接口电路包括具有输入共模电压的差分积分放大器和电压基本上等于输入共模电压的两个求和节点，用于将电容器充电到第一 电压电平在第一阶段中，在第二阶段将电容器连接到差分放大器的求和节点之一，以提供基本上代表第一电压电平和输入共模电压之间的差的第一输出变化，以及 也代表电容器; 在第三相中将电容器充电到第二电压电平，并且在第四相中将电容器连接到差分放大器的另一个求和节点，以提供基本上代表第二电压电平与第二电压之间的差的第二输出变化 输入共模电压，也代表电容器; 组合的第一和第二输出变化表示电容器的电容基本上独立于输入共模电压。
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公开(公告)号：US5987484A
公开(公告)日：1999-11-16
申请号：US56228
申请日：1998-04-07
申请人： Adrian Sherry , Damien McCartney , Michael Byrne
发明人： Adrian Sherry , Damien McCartney , Michael Byrne
IPC分类号： G06F17/10
CPC分类号： G06F17/10
摘要： A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.
摘要翻译： 数字滤波系统由输入信号馈送，并根据输入信号的时间变化率选择性地产生来自相对低带宽滤波器或相对宽带宽滤波器的输出信号。 当输入信号缓慢变化时，输出信号由相对较低带宽的滤波器产生，并且当输入信号快速变化时，输出信号由相对较宽的带宽滤波器产生，之后从较低带宽滤波器产生输出， 输入信号恢复到其更缓慢变化的特性。
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公开(公告)号：US5675334A
公开(公告)日：1997-10-07
申请号：US599811
申请日：1996-02-12
申请人： Damien McCartney
发明人： Damien McCartney
CPC分类号： H03M3/34 , H03M1/0663 , H03M1/12 , H03M3/464
摘要： An analog to digital conversion system wherein a first chopper is responsive to a chop signal having a period T for passing an analog signal to an output with non-reversed polarity during a first portion of the period T and with reversed polarity during a second portion of the period T. An analog to digital converter produces a first set of at least one digital word corresponding to the analog signal with non-reversed polarity and an offset voltage and produces a second set of at least one digital word corresponding to the analog signal with reversed polarity and the offset voltage. A second chopper is responsive to the chop signal for passing to an output of the second chopper one of the produced first and second sets with non-reversed polarity, and passing to the output of the second chopper the other one of produced first and second sets with reversed polarity. A filter is fed by the output of the second chopper for producing, on receipt of the produced first set, a first output digital word and, on receipt of the produced second set, a second output digital word, with the offset voltage being removed from each of such output digital words. In a preferred embodiment, a signal conditioning circuit is fed by the output of the first chopper.
摘要翻译： 一种模数转换系统，其中第一斩波器响应于具有周期T的斩波信号，该周期T用于在周期T的第一部分期间将模拟信号传递到具有非反相极性的输出，并且在第二部分期间具有相反的极性 模数转换器产生对应于具有非反相极性的模拟信号和偏移电压的至少一个数字字的第一组，并产生与模拟信号对应的至少一个数字字的第二组， 反极性和偏移电压。 第二斩波器响应于斩波信号，以非反相极性将所产生的第一和第二组中的一个输出到第二斩波器的输出，并且将第二斩波器的输出传递到所产生的第一和第二组中的另一个 反极性。 滤波器由第二斩波器的输出馈送，用于在接收到所产生的第一组时产生第一输出数字字，并且在接收到所产生的第二组时，产生第二输出数字字，其中偏移电压被从 每个这样的输出数字字。 在优选实施例中，信号调理电路由第一斩波器的输出馈送。
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9.发明授权
公开(公告)号：US4394685A
公开(公告)日：1983-07-19
申请号：US184079
申请日：1980-09-04
CPC分类号： H04N1/00291 , G06K15/10 , H04N1/00294 , H04N1/128 , H04N1/1911
摘要： An electronic interface for operating a dot matrix printer to print a pattern appearing on a television screen employs video-type signals incorporating field and line sync signals, digitized image signals representative of dots of information along each raster line and dot pulses for synchronizing the digitized image signals. Upon receipt of a print request, a line address counter is incremented by each line sync pulse. A second counter, which is incremented each time the line address counter reaches a maximum count, has its count set into a horizontal position counter at the beginning of each line scan and is decremented synchronously with the dot pulses. The sequentially received dot information is loaded serially into a shift register and is transferred byte-wise in parallel into a location in a random access memory identified by the count in the line address counter when the horizontal position counter reaches a zero count. When the line address counter reaches its maximum count, the interface circuitry prints the stored bytes, representing a "slice" of the raster image in an orientation transverse to the direction of the lines comprising the raster image. Successive "slices" are acquired and printed in a similar fashion to collectively create a completed image.
摘要翻译： 用于操作点阵打印机以打印出现在电视屏幕上的图案的电子接口使用包含场和行同步信号的视频类型信号，表示沿着每条光栅线的信息点的数字化图像信号和用于使数字化图像同步的点脉冲 信号。 在接收到打印请求时，行地址计数器由每行行同步脉冲递增。 每次线路地址计数器达到最大计数时递增的第二个计数器在每行扫描开始时将其计数设置为水平位置计数器，并与点脉冲同步递减。 顺序接收的点信息被串行地加载到移位寄存器中，并且当水平位置计数器达到零计数时，被逐行地并行地传送到由行地址计数器中的计数所标识的随机存取存储器中的位置。 当行地址计数器达到其最大计数时，接口电路以横向于包括光栅图像的线的方向的方向打印存储的字节，表示光栅图像的“切片”。 以相似的方式获取和打印连续的“切片”以共同创建完成的图像。
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10.发明授权Switched-capacitor one-bit digital-to-analog converter with low sensitivity to op-amp offset voltage 失效开关电容器1位数模转换器，对运放失调电压具有低灵敏度
公开(公告)号：US5563597A
公开(公告)日：1996-10-08
申请号：US254772
申请日：1994-06-06
申请人： Damien McCartney
发明人： Damien McCartney
摘要： A switched-capacitor DAC system includes an integrator circuit including an op amp having an input lead, an output lead and an integrator capacitor connected between the input lead and the output lead. A sampling switch is operable to connect an input capacitor to be charged by an input voltage during at least one of first and second non-overlapping time intervals, wherein the first time interval is subdivided into first and second non-overlapping sub-intervals and the second time interval is subdivided into third and fourth non-overlapping sub-intervals. A transferring switch is operable to connect the input capacitor to transfer charge from the input capacitor to transfer charge from the input capacitor to the integrator capacitor during at least one of the first and third sub-intervals. A discharging switch is operable to connect the input capacitor to a discharge node during at least one of the second and fourth sub-intervals. In a preferred embodiment of the present invention, the sampling switch connects the input capacitor during one of the first and second sub-intervals, the transferring switch connects the input capacitor during one of the first and third sub-intervals, and the discharging switch connects the input capacitor during one of the second and fourth sub-intervals.
摘要翻译： 开关电容器DAC系统包括积分器电路，其包括具有输入引线，输出引线和连接在输入引线和输出引线之间的积分电容器的运算放大器。 采样开关可操作以在第一和第二非重叠时间间隔中的至少一个期间连接要由输入电压充电的输入电容器，其中第一时间间隔被细分为第一和第二非重叠子间隔，并且 第二时间间隔被细分为第三和第四不重叠的子间隔。 转移开关可操作以在至少一个第一和第三子间隔期间连接输入电容器以从输入电容器传送电荷以将电荷从输入电容器传递到积分器电容器。 放电开关可操作以在第二和第四子间隔中的至少一个期间将输入电容器连接到放电节点。 在本发明的优选实施例中，采样开关在第一和第二子间隔之一期间连接输入电容器，转移开关在第一和第三子间隔之一期间连接输入电容器，并且放电开关连接 在第二和第四子间隔期间的输入电容器。
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