公开(公告)号：US07689966B2

公开(公告)日：2010-03-30

申请号：US11226698

申请日：2005-09-14

申请人： Gaurav Verma ,  Lance Glasser ,  Moshe E. Preil

发明人： Gaurav Verma ,  Lance Glasser ,  Moshe E. Preil

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： Various computer-implemented methods are provided. One method for evaluating reticle layout data includes generating a simulated image using the reticle layout data as input to a model of a reticle manufacturing process. The simulated image illustrates how features of the reticle layout data will be formed on a reticle by the reticle manufacturing process. The method also includes determining manufacturability of the reticle layout data using the simulated image. The manufacturability is a measure of how accurately the features will be formed on the reticle. Also provided are various carrier media that include program instructions executable on a computer system for performing a method for evaluating reticle layout data as described herein. In addition, systems configured to evaluate reticle layout data are provided. The systems include a computer system and a carrier medium that includes program instructions executable on the computer system for performing method(s) described herein.

摘要翻译： 提供了各种计算机实现的方法。 用于评估标线布局数据的一种方法包括使用标线布局数据作为对标线制造工艺的模型的输入来生成模拟图像。 模拟图像说明如何通过标线制造过程在掩模版上形成标线布局数据的特征。 该方法还包括使用模拟图像确定标线布局数据的可制造性。 可制造性是衡量在光罩上形成特征的准确度。 还提供了各种载体介质，其包括可在计算机系统上执行的程序指令，用于执行如本文所述的用于评估标线布局数据的方法。 此外，还提供了配置为评估标线布局数据的系统。 该系统包括计算机系统和载体介质，其包括可在计算机系统上执行以执行本文所述的方法的程序指令。

公开(公告)号：US20060062445A1

公开(公告)日：2006-03-23

申请号：US11226698

申请日：2005-09-14

申请人： Gaurav Verma ,  Lance Glasser ,  Moshe Preil

发明人： Gaurav Verma ,  Lance Glasser ,  Moshe Preil

IPC分类号： G06F17/50 ,  G06K9/00

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： Various computer-implemented methods are provided. One method for evaluating reticle layout data includes generating a simulated image using the reticle layout data as input to a model of a reticle manufacturing process. The simulated image illustrates how features of the reticle layout data will be formed on a reticle by the reticle manufacturing process. The method also includes determining manufacturability of the reticle layout data using the simulated image. The manufacturability is a measure of how accurately the features will be formed on the reticle. Also provided are various carrier media that include program instructions executable on a computer system for performing a method for evaluating reticle layout data as described herein. In addition, systems configured to evaluate reticle layout data are provided. The systems include a computer system and a carrier medium that includes program instructions executable on the computer system for performing method(s) described herein.

摘要翻译： 提供了各种计算机实现的方法。 用于评估标线布局数据的一种方法包括使用标线布局数据作为对标线制造工艺的模型的输入来生成模拟图像。 模拟图像说明如何通过标线制造过程在掩模版上形成标线布局数据的特征。 该方法还包括使用模拟图像确定标线布局数据的可制造性。 可制造性是衡量在光罩上形成特征的准确度。 还提供了各种载体介质，其包括可在计算机系统上执行的程序指令，用于执行如本文所述的用于评估标线布局数据的方法。 此外，还提供了配置为评估标线布局数据的系统。 该系统包括计算机系统和载体介质，其包括可在计算机系统上执行以执行本文所述的方法的程序指令。

公开(公告)号：US08603628B2

公开(公告)日：2013-12-10

申请号：US11742220

申请日：2007-04-30

申请人： Gaurav Verma ,  Vincent Garreau

发明人： Gaurav Verma ,  Vincent Garreau

IPC分类号： B32B37/30 ,  B32B27/00

CPC分类号： F03D1/065 ,  F05B2230/90 ,  F05B2280/4003 ,  F05B2280/6011 ,  F05C2225/00 ,  F05C2253/12 ,  F15D1/0035 ,  Y02E10/721 ,  Y02P70/523 ,  Y10T428/28 ,  Y10T428/3154

摘要： A method of manufacturing a turbine blade includes providing a multilayer polymeric film. The multilayer polymeric film includes a first layer including an acrylic-based adhesive, a second layer disposed over the first layer, and a third layer disposed over the second layer. The second layer includes a blend of an acrylic polymer and fluoropolymer. The third layer has at least a portion with a smooth surface. The third layer includes fluoropolymer. The method further includes laminating the multilayer polymeric film over at least a portion of a turbine blade work piece. The first layer contacts the turbine blade work piece.

摘要翻译： 制造涡轮叶片的方法包括提供多层聚合物膜。 多层聚合物膜包括第一层，其包括丙烯酸类粘合剂，设置在第一层上的第二层和设置在第二层上的第三层。 第二层包括丙烯酸聚合物和含氟聚合物的共混物。 第三层具有至少一部分具有光滑表面的部分。 第三层包括含氟聚合物。 该方法还包括在涡轮叶片工件的至少一部分上层叠多层聚合物膜。 第一层接触涡轮叶片工件。

公开(公告)号：US20120273072A1

公开(公告)日：2012-11-01

申请号：US13492477

申请日：2012-06-08

申请人： Rajesh Kelekar ,  Gaurav Verma ,  Kurt Weiner

发明人： Rajesh Kelekar ,  Gaurav Verma ,  Kurt Weiner

IPC分类号： B67D7/02

CPC分类号： G01F22/02 ,  Y10T137/86035

摘要： A pressure gauge may be coupled to a vessel into which a liquid chemical is to be dispensed. The volume of the vessel may be known and a control device may determine an initial pressure of the vessel using the pressure gauge. A volume of liquid chemical may be dispensed into the vessel which may cause the pressure within the vessel to increase to a second pressure. The control device may determine the second pressure using the pressure gauge may calculate the volume of liquid chemical dispensed into the vessel using the volume of the vessel, the initial pressure of the vessel, and the second pressure of the vessel.

摘要翻译： 压力计可以连接到要分配液体化学品的容器中。 容器的体积可以是已知的，并且控制装置可以使用压力计来确定容器的初始压力。 液体化学品的体积可以分配到容器中，这可能导致容器内的压力增加到第二压力。 控制装置可以使用压力计来确定第二压力可以使用容器的体积，容器的初始压力和容器的第二压力来计算分配到容器中的液体化学品的体积。

公开(公告)号：US07824935B2

公开(公告)日：2010-11-02

申请号：US12167118

申请日：2008-07-02

申请人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

发明人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

IPC分类号： H01L21/00

CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。

公开(公告)号：US07493590B1

公开(公告)日：2009-02-17

申请号：US11549943

申请日：2006-10-16

申请人： Carl Hess ,  Ruifang Shi ,  Gaurav Verma

发明人： Carl Hess ,  Ruifang Shi ,  Gaurav Verma

IPC分类号： G06F17/50 ,  G06F19/00 ,  G06F17/17 ,  G03F1/00 ,  G21K5/00

CPC分类号： G03F1/36

摘要： Optical proximity correction methods and apparatus are disclosed. A simulated geometry representing one or more printed features from a reticle is generated using an optical proximity correction (OPC) model that takes into account a reticle design and one or more parameters from a process window of a stepper. An error function is formed that measures a deviation between the simulated geometry and a desired design of the one or more printed features. The error function takes into account parameters (p0 . . . pJ) from across the process window in addition to, or in lieu of, a best focus and a best exposure for the stepper. The reticle design is adjusted in a way that reduces the deviation as measured by the error function, thereby producing an adjusted reticle design.

摘要翻译： 公开了光学邻近校正方法和装置。 使用光学邻近校正（OPC）模型来生成表示来自光罩的一个或多个印刷特征的模拟几何，其考虑到来自步进机的过程窗口的掩模版设计和一个或多个参数。 形成误差函数，其测量模拟几何与所述一个或多个印刷特征的期望设计之间的偏差。 除了代替步进器的最佳焦点和最佳曝光之外，误差函数还考虑了过程窗口中的参数（p0。。pJ）。 以通过误差函数测量的方式减小偏差的方法调整掩模版设计，从而产生调整的掩模版设计。

公开(公告)号：US07280945B1

公开(公告)日：2007-10-09

申请号：US10187567

申请日：2002-07-01

申请人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

发明人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

IPC分类号： G06F17/10 ,  G06F17/50

CPC分类号： G01R31/318364

摘要： Disclosed are mechanisms are provided for determining whether a particular integrated circuit (IC) pattern is susceptible to systematic failure, e.g., due to process fluctuations. In one embodiment, final resist patterns for such IC pattern are simulated using a sparse type simulator under various process settings. The sparse type simulator uses a model (e.g., a variable threshold resist model) for a particular photolithography process in which the IC pattern is to be fabricated. The model is generated from measurements taken from a plurality of simulated structures output from a rigorous type simulator. The simulated final resist patterns may then be analyzed to determine whether the corresponding IC pattern is susceptible to systematic failure. After an IC pattern which is susceptible to systematic failure has been found, a test structure may be fabricated from a plurality of IC patterns or cells. The cells of the test structure are arranged to have a particular pattern of voltage potential or brightness levels during a voltage contrast inspection. Mechanisms for quickly inspecting such test structures to thereby predict systematic yield of a product device containing patterns similar to the test structure cells are also disclosed.

摘要翻译： 公开了提供用于确定特定集成电路（IC）模式是否易于系统故障（例如由于过程波动）的机制。 在一个实施例中，使用在各种处理设置下的稀疏型模拟器来模拟这种IC图案的最终抗蚀剂图案。 稀疏型模拟器对于要制造IC图案的特定光刻工艺使用模型（例如，可变阈值抗蚀剂模型）。 该模型是从从严格型模拟器输出的多个模拟结构中获得的测量产生的。 然后可以分析模拟的最终抗蚀剂图案，以确定相应的IC图案是否易于发生系统故障。 在已经发现容易发生系统故障的IC图案之后，可以从多个IC图案或单元制造测试结构。 测试结构的单元被布置成在电压对比度检查期间具有电压电位或亮度水平的特定图案。 还公开了用于快速检查这种测试结构从而预测包含类似于测试结构单元的图案的产品设备的系统产量的机制。

公开(公告)号：US08343327B2

公开(公告)日：2013-01-01

申请号：US12787330

申请日：2010-05-25

申请人： Kurt H. Weiner ,  Gaurav Verma

发明人： Kurt H. Weiner ,  Gaurav Verma

IPC分类号： C25D5/10 ,  C25D5/00 ,  C25D17/00

CPC分类号： C25D5/022 ,  C25D5/08 ,  C25D17/001 ,  C25D17/005 ,  C25D17/12

摘要： The invention relates generally to electrodeposition apparatus and methods. When depositing films via electrodeposition, where the substrate has an inherent resistivity, for example, sheet resistance in a thin film, methods and apparatus of the invention are used to electrodeposit materials onto the substrate by forming a plurality of ohmic contacts to the substrate surface and thereby overcome the inherent resistance and electrodeposit uniform films. Methods and apparatus of the invention find particular use in solar cell fabrication.

摘要翻译： 本发明一般涉及电沉积装置和方法。 当通过电沉积沉积膜时，其中衬底具有固有电阻率，例如薄膜中的薄层电阻，本发明的方法和装置用于通过在衬底表面上形成多个欧姆接触将材料电沉积到衬底上， 从而克服固有的电阻和电沉积均匀的膜。 本发明的方法和装置在太阳能电池制造中特别有用。

公开(公告)号：US08220502B1

公开(公告)日：2012-07-17

申请号：US11966654

申请日：2007-12-28

申请人： Rajesh Kelekar ,  Gaurav Verma ,  Kurt Weiner

发明人： Rajesh Kelekar ,  Gaurav Verma ,  Kurt Weiner

IPC分类号： G01F22/02

CPC分类号： G01F22/02 ,  Y10T137/86035

摘要： A pressure gauge may be coupled to a vessel into which a liquid chemical is to be dispensed. The volume of the vessel may be known and a control device may determine an initial pressure of the vessel using the pressure gauge. A volume of liquid chemical may be dispensed into the vessel which may cause the pressure within the vessel to increase to a second pressure. The control device may determine the second pressure using the pressure gauge may calculate the volume of liquid chemical dispensed into the vessel using the volume of the vessel, the initial pressure of the vessel, and the second pressure of the vessel.

摘要翻译： 压力计可以连接到要分配液体化学品的容器中。 容器的体积可以是已知的，并且控制装置可以使用压力计来确定容器的初始压力。 液体化学品的体积可以分配到容器中，这可能导致容器内的压力增加到第二压力。 控制装置可以使用压力计来确定第二压力可以使用容器的体积，容器的初始压力和容器的第二压力来计算分配到容器中的液体化学品的体积。

公开(公告)号：US20110248264A1

公开(公告)日：2011-10-13

申请号：US12905945

申请日：2010-10-15

申请人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

发明人： Gaurav Verma ,  Kurt Weiner ,  Prashant Phatak ,  Imran Hashim ,  Sandra Malhotra ,  Tony Chiang

IPC分类号： H01L29/66

CPC分类号： G01R31/2831 ,  G01R31/2834 ,  H01L22/34

摘要： In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

摘要翻译： 在本发明的实施例中，描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料，工艺和工艺顺序集成方案。 通常，这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序，使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料，工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域，其中每个区域彼此变化，并且测试芯片被设计为能够实现不同区域的高通量测试。