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    High aspect ratio and reduced undercut trench etch process for a semiconductor substrate
    3.
    发明授权
    High aspect ratio and reduced undercut trench etch process for a semiconductor substrate 有权
    用于半导体衬底的高纵横比和减少的底切沟槽蚀刻工艺

    公开(公告)号：US08652969B2

    公开(公告)日：2014-02-18

    申请号：US13281715

    申请日：2011-10-26

    申请人： Nicholas C. M. Fuller ,  Eric A. Joseph ,  Edmund M. Sikorski ,  Goh Matsuura

    发明人： Nicholas C. M. Fuller ,  Eric A. Joseph ,  Edmund M. Sikorski ,  Goh Matsuura

    IPC分类号： H01L21/768 ,  H01L23/00

    CPC分类号： H01L29/0657 ,  H01L21/30655 ,  H01L21/76898

    摘要： A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.

    摘要翻译： 在各向异性蚀刻工艺中使用氢氟烃气体作为聚合物沉积气体，其使用蚀刻剂气体和聚合物沉积气体的交替来蚀刻半导体衬底中的深沟槽。 氢氟烃气体可以在半导体衬底的顶表面上与聚合物的厚度一致的厚度在沟槽的侧壁上产生厚的富碳和含氢聚合物。 厚的富碳和含氢聚合物保护沟槽的侧壁，从而使硬掩模下方的底切最小化，而不降低整体速率。 在一些实施例中，可以实现整体蚀刻速率的改进。

    Phase change memory device with plated phase change material
    6.
    发明授权
    Phase change memory device with plated phase change material 有权
    相变存储器件，具有电镀相变材料

    公开(公告)号：US08030130B2

    公开(公告)日：2011-10-04

    申请号：US12541595

    申请日：2009-08-14

    申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Alejandro G. Schrott ,  Xiaoyan Shao

    发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Alejandro G. Schrott ,  Xiaoyan Shao

    IPC分类号： H01L21/06

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1683 ,  H01L45/1691

    摘要： A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.

    摘要翻译： 一种用于制造包括存储单元的相变存储器件的方法包括将通孔图案化成与要连接到存取电路的导电触头阵列相对应的衬底的接触表面，将每个通孔用保形导电晶种层 形成覆盖导电种子层的电介质层，并将每个通孔的中心区域蚀刻到接触表面，以在接触表面露出共形导电种子层。 该方法还包括在保形导电晶种层的暴露部分上电镀相变材料，使形成导电材料的中心区域内的相变材料凹陷在凹陷相变材料上，该导电材料在凹陷相变材料上保持导电，保形导电 晶种层沿每个通孔的侧面形成，并且在每个存储单元上形成顶部电极。

    Self aligned ring electrodes
    7.
    发明授权
    Self aligned ring electrodes 有权
    自对准环形电极

    公开(公告)号：US07981755B2

    公开(公告)日：2011-07-19

    申请号：US11924073

    申请日：2007-10-25

    申请人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Alejandro G. Schrott ,  Brandon Yee

    发明人： Matthew J. Breitwisch ,  Eric A. Joseph ,  Chung H. Lam ,  Alejandro G. Schrott ,  Brandon Yee

    IPC分类号： H01L21/331 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

    摘要： The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.

    摘要翻译： 本发明在一个实施例中提供了一种制造电极的方法，其包括提供定位在延伸到第一介电层中的通孔中的至少一个金属柱，其中导电衬垫定位在通孔的至少侧壁和在 最少一个金属螺柱; 将所述至少一个金属螺柱的上表面凹陷在所述第一介电层的上表面下方，以提供至少一个凹入的金属柱; 以及在所述至少一个凹入的金属螺柱的顶部上形成第二电介质，其中所述导电衬垫的上表面被暴露。

    PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    9.
    发明申请
    PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权
    用于磁阻随机存取存储器的基于柱状的互连

    公开(公告)号：US20110049655A1

    公开(公告)日：2011-03-03

    申请号：US12549799

    申请日：2009-08-28

    申请人： Solomon Assefa ,  Michael C. Gaidis ,  Eric A. Joseph ,  Eugene J. O'Sullivan

    发明人： Solomon Assefa ,  Michael C. Gaidis ,  Eric A. Joseph ,  Eugene J. O'Sullivan

    IPC分类号： H01L43/08 ,  H01L43/12

    CPC分类号： H01L43/12 ,  H01L27/222 ,  H01L43/08

    摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.

    摘要翻译： 半导体器件包括包括M2图案化区域的衬底。 在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。 在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。

    THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS
    10.
    发明申请
    THERMALLY INSULATED PHASE CHANGE MATERIAL CELLS 有权
    热绝缘相变材料

    公开(公告)号：US20110001111A1

    公开(公告)日：2011-01-06

    申请号：US12497596

    申请日：2009-07-03

    申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Blpin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

    发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Eric A. Joseph ,  Chung H. Lam ,  Blpin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

    IPC分类号： H01L45/00 ,  H01L21/06

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

    摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

    摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。