公开(公告)号：US4751634A

公开(公告)日：1988-06-14

申请号：US744851

申请日：1985-06-14

申请人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  Mario A. Marsico ,  John C. Pescatore ,  Paul D. Sullivan

发明人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  Mario A. Marsico ,  John C. Pescatore ,  Paul D. Sullivan

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/12 ,  G06F13/34 ,  G06F13/32

CPC分类号： G06F13/34

摘要： A multi-port communications controller and variable protocol adapter is described. The adapter utilizes a user programmable pluggable programming cartridge for defining individual communications port data service characteristics. The port data service characteristics are interpreted by a microprocessor which manages the interchange from port to port and to or from memory or a host system. Direct memory access or interrupt driven memory access modes of operation are individually selectable for each individual in bound and out bound communications channel. The communications protocols employed at each port may be of any standard type with the microprocessor in the adapter making the appropriate conversion. Communication speeds can be automatically recognized and matched for each port also. An arbitration processor for both DMA and interrupt driven data transfer services is included as the heart of the communications adapter design to provide the capability of individualized control over each in bound and out bound channel's mode of data transfer service for the optimum mode of operation for each port and type of data service required.

摘要翻译： 描述了多端口通信控制器和可变协议适配器。 适配器使用用户可编程可插拔编程盒来定义各个通信端口数据服务特性。 端口数据服务特性由管理从端口到端口以及存储器或主机系统之间的交换的微处理器来解释。 直接存储器访问或中断驱动存储器访问操作模式可以在绑定和绑定的通信通道中为每个人分别选择。 每个端口采用的通信协议可以是任何标准类型，适配器中的微处理器进行适当的转换。 通信速度也可以自动识别并匹配每个端口。 包括DMA和中断驱动数据传输服务的仲裁处理器被包括为通信适配器设计的核心，以提供在绑定和绑定信道的数据传输服务模式中的每一个的个性化控制的能力，以实现每个 所需的数据服务的端口和类型。

公开(公告)号：US4837677A

公开(公告)日：1989-06-06

申请号：US744850

申请日：1985-06-14

申请人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  Mario A. Marsico ,  John C. Pescatore ,  Paul D. Sullivan

发明人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  Mario A. Marsico ,  John C. Pescatore ,  Paul D. Sullivan

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/12 ,  G06F13/34

CPC分类号： G06F13/34

摘要： Bus interconnection between the system busses of a multi-port communications controller and the busses of one or more multi-port adapters is facilitated with a new architecture for providing an interconnection controller. A programmably adjustable adapter and port interface controller is combined via a scannerless communications controller with a bus interconnection control logic that handles both DMA and interrupt mode data transfers for a large number of channels. The invention provides an improved apparatus and method for transferring data to or from numerous communication channel devices within a processor based communications system in such a manner that the optimum mode of data transfer may be individually programmed for each channel as system environment conditions demand.

摘要翻译： 用于提供互连控制器的新架构便于多端口通信控制器的系统总线与一个或多个多端口适配器的总线之间的总线互连。 可编程调节的适配器和端口接口控制器通过无扫描器通信控制器与总线互连控制逻辑组合，总线互连控制逻辑可处理大量通道的DMA和中断模式数据传输。 本发明提供了一种用于在基于处理器的通信系统内向多个通信信道设备传送数据或从多个通信信道设备传送数据的改进的设备和方法，使得可以根据系统环境条件要求为每个信道单独编程数据传输的最佳模式。

公开(公告)号：US4716523A

公开(公告)日：1987-12-29

申请号：US744852

申请日：1985-06-14

申请人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  John C. Pescatore ,  Mario A. Marsico

发明人： Gilbert S. Burrus, Jr. ,  Ronald J. Cooper ,  Michael R. Marr ,  John C. Pescatore ,  Mario A. Marsico

IPC分类号： H04L29/04 ,  G06F13/00 ,  G06F13/12 ,  G06F13/34 ,  G06F13/32

CPC分类号： G06F13/34

摘要： Both DMA access and character interrupt driven access modes of service are provided to multiple communication ports by an integrated arbitration DMA/interrupt controller utilizing its own resident randomly accessible memory. Pipelined logic control architecture for handling service mode adaptations for each individual port and for managing memory accesses to main system memory enables the use of the random access memory with its inherent time delays in a manner that virtually eliminates the effect of any time delay in overall memory access throughput.

摘要翻译： DMA访问和字符中断驱动的访问服务模式都通过集成的仲裁DMA /中断控制器提供给多个通信端口，该仲裁DMA /中断控制器利用其本身的随机可访问存储器。 用于处理每个单独端口的服务模式适配和用于管理对主系统存储器的存储器访问的流水线逻辑控制架构使得能够以其固有的时间延迟来使用随机存取存储器，其方式实际上消除了整个存储器中的任何时间延迟的影响 访问吞吐量。

公开(公告)号：US4648029A

公开(公告)日：1987-03-03

申请号：US644882

申请日：1984-08-27

申请人： Ronald J. Cooper ,  Mario A. Marsico ,  John C. Pescatore ,  Paul D. Sullivan

发明人： Ronald J. Cooper ,  Mario A. Marsico ,  John C. Pescatore ,  Paul D. Sullivan

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/10 ,  G06F11/22 ,  G06F11/267 ,  G06F13/34 ,  G06F13/362 ,  G06F15/177 ,  G06F9/46 ,  G06F13/18 ,  G06F13/24 ,  G06F13/36

CPC分类号： G06F13/34 ,  G06F11/1044 ,  G06F11/2205 ,  G06F11/2221

摘要： In an arbitration apparatus and technique, the request lines from a plurality of potential requestors serve both as interrupt and DMA bus request signal lines to an arbitration device. The arbitration device selects among contending requestors on a priority basis and generates a grant signal interpreted by the requesting devices either as an interrupt grant or a bus grant depending upon whether or not an interrupt acknowledge signal is received. This effectively multiplexes the grant request lines from a plurality of requestors to greatly reduce interconnection complexity and cost. A single interrupt grant/bus grant multi-wire signal cable connects from the arbitration device to the individual requestors. A grant will appear on a single line thereof connected to an individual requestor that has been granted either an interrupt or access to the bus. Interrupt requests from the requestors are ORed together and simultaneously presented to a central controlling microprocessor. The arbitration device determines which requestor will be granted access and, under control of the central control microprocessor, the arbitrator gates an interrupt grant or a DMA grant signal to the device selected by the arbitration mechanism. The dual usage of the grant and request lines by the arbitration device represents a multiplexing feature to further reduce interconnections.

摘要翻译： 在仲裁装置和技术中，来自多个潜在请求者的请求线同时用作中断和DMA总线请求信号线到仲裁装置。 仲裁装置在竞争请求者中优先选择，并且根据是否接收到中断确认信号，生成作为中断授权或总线许可的请求装置解释的授权信号。 这有效地多路复用来自多个请求者的授权请求线，以大大降低互连的复杂性和成本。 单个中断授权/总线授权多线信号电缆从仲裁设备连接到各个请求者。 授权将出现在连接到被授予中断或访问总线的个人请求者的单个线路上。 来自请求者的中断请求被OR并入并同时呈现给中央控制微处理器。 仲裁设备确定哪个请求者将被授权访问，并且在中央控制微处理器的控制下，仲裁者将中断授权或DMA授权信号锁定到由仲裁机制选择的设备。 仲裁设备对授权和请求行的双重使用表示多路复用功能，以进一步减少互连。

公开(公告)号：US4627054A

公开(公告)日：1986-12-02

申请号：US644888

申请日：1984-08-27

申请人： Ronald J. Cooper ,  Mario A. Marsico ,  John C. Pescatore

发明人： Ronald J. Cooper ,  Mario A. Marsico ,  John C. Pescatore

IPC分类号： G06F11/16 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/22 ,  G06F11/267 ,  G06F13/36 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F11/00 ,  G06F11/1044 ,  G06F11/2205 ,  G06F11/2221

摘要： A multiprocessor array is described in which a central controlling microprocessor interfaces over commonly connected address and data busses to a plurality of peripheral microprocessors. A memory mapped I/O interface controls access to and from the busses for mutual receipt and exchange of signals between the processors and mutual exchange and receipt of data among the processors. The individual processors are selectively isolatable by a plurality of three state switch means connected between each processor and the interconnecting data and address busses. Error detection and control logic is connected via control lines to the individual processors and responsive to an error indication thereof, activates a multipoint error signal to all said microprocessors over a control line, which signal is interpreted by the processor then controlling said busses as a signal to deactivate its operation and as a signal at said control microprocessor to invoke an interrupt for analyzing the causes of said error. The control microprocessor can issue memory mapped I/O instructions to the individual three state selective isolation means and/or to any of the I/O microprocessors to respectively isolate the processors from said busses or to control said processors in an error analysis routine. The apparatus further includes a machine check register and a bus master register associated with said control microprocessor which registers can be written in by said control microprocessor and read from only by one of said I/O microprocessors.

摘要翻译： 描述了一种多处理器阵列，其中中央控制微处理器将共同连接的地址和数据总线连接到多个外围微处理器。 存储器映射的I / O接口控制对总线的访问以便在处理器之间相互接收和交换信号，并且在处理器之间相互交换和接收数据。 各个处理器由连接在每个处理器和互连数据和地址总线之间的多个三态开关装置选择性隔离。 错误检测和控制逻辑经由控制线路连接到各个处理器并且响应于其错误指示，通过控制线路激活对所有所述微处理器的多点误差信号，该处理器解释该信号，然后控制所述总线作为信号 以使其操作失效并作为所述控制微处理器处的信号来调用中断来分析所述错误的原因。 控制微处理器可以向各个三态选择性隔离装置和/或任何I / O微处理器发出存储器映射I / O指令，以将处理器与所述总线分开隔离或者在错误分析程序中控制所述处理器。 该装置还包括机器检查寄存器和与所述控制微处理器相关联的总线主寄存器，该寄存器可由所述控制微处理器写入，并且仅由所述I / O微处理器之一读取。

公开(公告)号：US4870566A

公开(公告)日：1989-09-26

申请号：US644889

申请日：1984-08-27

申请人： Ronald J. Cooper ,  Mario A. Marsico ,  Richard C. Matlack, Jr. ,  John C. Pescatore ,  Robert L. Smith, Jr.

发明人： Ronald J. Cooper ,  Mario A. Marsico ,  Richard C. Matlack, Jr. ,  John C. Pescatore ,  Robert L. Smith, Jr.

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F13/00 ,  G06F13/12 ,  G06F13/26 ,  G06F13/28 ,  G06F13/32 ,  G06F13/364 ,  H04L5/22 ,  H04L29/00 ,  H04L29/02

CPC分类号： G06F11/2221 ,  G06F11/00 ,  G06F13/124 ,  G06F13/26 ,  G06F13/28 ,  G06F13/364 ,  G06F11/10 ,  G06F11/2205 ,  G06F11/2294

摘要： A communications concentrator and message multiplexer featuring direct access from the communications adapters to main memory via direct memory access means which eliminates the usual scanner or polling facility in a concentrator or multiplexer is described. A control microprocessor manages the allocation of memory, the conversion of message protocols and the servicing of interrupts to a plurality of port interface adapter microprocessors. The interface adapter microprocessors directly set up and control the DMA operation instead of having the DMA operation controlled by the control processor. One of the port adapters serves as a service adapter over a dedicated interface allowing a remote disgnostician access to internal registers in the control processor system, access to a dedicated read only storage for servicing, and logical interface to the main control processor for the purpose of entering instructions and directing functional operations to test each component of the system.

摘要翻译： 描述了一种通信集中器和消息多路复用器，其特征在于通过直接存储器访问装置直接从通信适配器访问主存储器，其消除了集中器或多路复用器中通常的扫描器或轮询设备。 控制微处理器管理存储器的分配，消息协议的转换和中断服务到多个端口接口适配器微处理器。 接口适配器微处理器直接设置和控制DMA操作，而不是由控制处理器控制DMA操作。 其中一个端口适配器通过专用接口用作服务适配器，允许远程监控员访问控制处理器系统中的内部寄存器，访问专用的只读存储器进行维修，以及与主控制器的逻辑接口，用于 输入指令并指导功能操作来测试系统的每个组件。