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1.
公开(公告)号:US08957476B2
公开(公告)日:2015-02-17
申请号:US13722801
申请日:2012-12-20
IPC分类号: H01L21/8234 , H01L27/088
CPC分类号: H01L29/16 , H01L21/823431 , H01L27/0886 , H01L29/0669 , H01L29/1033 , H01L29/785 , H01L29/7853
摘要: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
摘要翻译: 本公开的实施例提供了与从硅(Si)到硅锗(SiGe)的薄晶体管元件的转换相关联的技术和配置。 在一个实施例中,一种方法包括提供具有设置在半导体衬底上的晶体管器件的沟道体的半导体衬底,沟道体包括硅,在沟道本体上形成包含锗的包覆层,并使通道体退火, 锗扩散到通道体内。 可以描述和/或要求保护其他实施例。
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2.
公开(公告)号:US20140175543A1
公开(公告)日:2014-06-26
申请号:US13722801
申请日:2012-12-20
IPC分类号: H01L21/8234 , H01L27/088
CPC分类号: H01L29/16 , H01L21/823431 , H01L27/0886 , H01L29/0669 , H01L29/1033 , H01L29/785 , H01L29/7853
摘要: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
摘要翻译: 本公开的实施例提供了与从硅(Si)到硅锗(SiGe)的薄晶体管元件的转换相关联的技术和配置。 在一个实施例中,一种方法包括提供具有设置在半导体衬底上的晶体管器件的沟道体的半导体衬底,沟道体包括硅,在沟道本体上形成包含锗的包覆层,并使通道体退火, 锗扩散到通道体内。 可以描述和/或要求保护其他实施例。
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公开(公告)号:US09728464B2
公开(公告)日:2017-08-08
申请号:US13560513
申请日:2012-07-27
IPC分类号: H01L21/335 , H01L21/8238 , H01L29/10
CPC分类号: H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L29/1054
摘要: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
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4.
公开(公告)号:US20140027860A1
公开(公告)日:2014-01-30
申请号:US13560513
申请日:2012-07-27
IPC分类号: H01L27/088 , H01L21/336
CPC分类号: H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L29/1054
摘要: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
摘要翻译: 公开了用于定制鳍式晶体管器件以提供同一集成电路管芯内的不同范围的通道配置和/或材料系统的技术。 根据一个示例性实施例,除去牺牲翅片并用适合于给定应用的任意组合和应变的定制半导体材料代替。 在一种这样的情况下,第一组牺牲翅片中的每一个凹陷或以其它方式移除并用p型材料代替,并且第二组牺牲翅片中的每一个凹入或以其它方式移除并且用n型 材料。 p型材料可以完全独立于n型材料的工艺,反之亦然。 使用本文提供的技术可实现许多其它电路配置和设备变化。
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公开(公告)号:US20140027816A1
公开(公告)日:2014-01-30
申请号:US13560474
申请日:2012-07-27
申请人: Stephen M. Cea , Anand S. Murthy , Glenn A. Glass , Daniel B. Aubertine , Tahir Ghani , Jack T. Kavalieros , Roza Kotlyar
发明人: Stephen M. Cea , Anand S. Murthy , Glenn A. Glass , Daniel B. Aubertine , Tahir Ghani , Jack T. Kavalieros , Roza Kotlyar
IPC分类号: H01L29/78 , H01L29/165
CPC分类号: H01L29/1054 , H01L21/76224 , H01L29/06 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
摘要翻译: 公开了用于将高迁移率应变通道结合到鳍状晶体管(例如,诸如双栅极,三相等等的FinFET)中的技术,其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中,硅锗(SiGe)被包覆到硅散热片上以提供期望的应力,尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容,并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下,来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下,可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中,硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。
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公开(公告)号:US08847281B2
公开(公告)日:2014-09-30
申请号:US13560474
申请日:2012-07-27
申请人: Stephen M. Cea , Anand S. Murthy , Glenn A. Glass , Daniel B. Aubertine , Tahir Ghani , Jack T. Kavalieros , Roza Kotlyar
发明人: Stephen M. Cea , Anand S. Murthy , Glenn A. Glass , Daniel B. Aubertine , Tahir Ghani , Jack T. Kavalieros , Roza Kotlyar
IPC分类号: H01L29/165
CPC分类号: H01L29/1054 , H01L21/76224 , H01L29/06 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851
摘要: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
摘要翻译: 公开了用于将高迁移率应变通道结合到鳍状晶体管(例如,诸如双栅极,三相等等的FinFET)中的技术,其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中,硅锗(SiGe)被包覆到硅散热片上以提供期望的应力,尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容,并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下,来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下,可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中,硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。
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公开(公告)号:US20130161756A1
公开(公告)日:2013-06-27
申请号:US13560531
申请日:2012-07-27
IPC分类号: H01L27/092 , H01L21/8238
CPC分类号: H01L29/0676 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7855 , H01L29/78696
摘要: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
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公开(公告)号:US09012284B2
公开(公告)日:2015-04-21
申请号:US13560531
申请日:2012-07-27
IPC分类号: H01L21/8238 , H01L27/092 , H01L29/66 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号: H01L29/0676 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7855 , H01L29/78696
摘要: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
摘要翻译: 公开了用于定制纳米线晶体管器件以提供同一集成电路管芯内的不同范围的通道配置和/或材料系统的技术。 根据一个示例性实施例,除去牺牲翅片并用适合于给定应用的任意组合和应变的定制材料堆叠代替。 在一种这样的情况下,第一组牺牲散热片中的每一个凹陷或以其它方式移除并被p型层堆叠代替,并且第二组牺牲散热片中的每一个凹进或以其它方式移除, 类型层堆栈。 p型层堆栈可以完全独立于n型层堆栈的过程,反之亦然。 使用本文提供的技术可实现许多其它电路配置和设备变化。
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公开(公告)号:US20160086951A1
公开(公告)日:2016-03-24
申请号:US14948083
申请日:2015-11-20
申请人: Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
发明人: Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
IPC分类号: H01L27/092 , H01L21/8238 , H01L29/423 , H01L29/06 , H01L29/10
CPC分类号: H01L21/823821 , B82Y10/00 , H01L21/8238 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L27/1211 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
摘要翻译: 描述了免费的金属氧化物半导体纳米线结构。 例如,半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点,并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点,并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。
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公开(公告)号:US09224810B2
公开(公告)日:2015-12-29
申请号:US13996503
申请日:2011-12-23
申请人: Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
发明人: Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
IPC分类号: H01L29/06 , H01L21/8238 , H01L27/092 , H01L27/12 , B82Y10/00 , H01L29/66 , H01L29/775
CPC分类号: H01L21/823821 , B82Y10/00 , H01L21/8238 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L27/1211 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
摘要翻译: 描述了免费的金属氧化物半导体纳米线结构。 例如,半导体结构包括第一半导体器件。 第一半导体器件包括设置在衬底之上的第一纳米线。 第一纳米线具有在衬底上方的第一距离的中点,并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。 第一栅极电极堆叠完全包围第一纳米线的离散通道区域。 半导体结构还包括第二半导体器件。 第二半导体器件包括设置在衬底上方的第二纳米线。 第二纳米线在衬底上方具有第二距离的中点,并且在离散通道区域的任一侧上包括离散通道区域和源极和漏极区域。 第一距离与第二距离不同。 第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。
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