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公开(公告)号：US09012284B2
公开(公告)日：2015-04-21
申请号：US13560531
申请日：2012-07-27
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/66 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/0676 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7855 , H01L29/78696
摘要： Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
摘要翻译： 公开了用于定制纳米线晶体管器件以提供同一集成电路管芯内的不同范围的通道配置和/或材料系统的技术。 根据一个示例性实施例，除去牺牲翅片并用适合于给定应用的任意组合和应变的定制材料堆叠代替。 在一种这样的情况下，第一组牺牲散热片中的每一个凹陷或以其它方式移除并被p型层堆叠代替，并且第二组牺牲散热片中的每一个凹进或以其它方式移除， 类型层堆栈。 p型层堆栈可以完全独立于n型层堆栈的过程，反之亦然。 使用本文提供的技术可实现许多其它电路配置和设备变化。
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公开(公告)号：US20130161756A1
公开(公告)日：2013-06-27
申请号：US13560531
申请日：2012-07-27
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L29/0676 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7855 , H01L29/78696
摘要： Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
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公开(公告)号：US09728464B2
公开(公告)日：2017-08-08
申请号：US13560513
申请日：2012-07-27
IPC分类号： H01L21/335 , H01L21/8238 , H01L29/10
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L29/1054
摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
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公开(公告)号：US08847281B2
公开(公告)日：2014-09-30
申请号：US13560474
申请日：2012-07-27
申请人： Stephen M. Cea , Anand S. Murthy , Glenn A. Glass , Daniel B. Aubertine , Tahir Ghani , Jack T. Kavalieros , Roza Kotlyar
发明人： Stephen M. Cea , Anand S. Murthy , Glenn A. Glass , Daniel B. Aubertine , Tahir Ghani , Jack T. Kavalieros , Roza Kotlyar
IPC分类号： H01L29/165
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/06 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
摘要翻译： 公开了用于将高迁移率应变通道结合到鳍状晶体管（例如，诸如双栅极，三相等等的FinFET）中的技术，其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中，硅锗（SiGe）被包覆到硅散热片上以提供期望的应力，尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下，来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下，可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中，硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。
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公开(公告)号：US20140175543A1
公开(公告)日：2014-06-26
申请号：US13722801
申请日：2012-12-20
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L29/16 , H01L21/823431 , H01L27/0886 , H01L29/0669 , H01L29/1033 , H01L29/785 , H01L29/7853
摘要： Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例提供了与从硅（Si）到硅锗（SiGe）的薄晶体管元件的转换相关联的技术和配置。 在一个实施例中，一种方法包括提供具有设置在半导体衬底上的晶体管器件的沟道体的半导体衬底，沟道体包括硅，在沟道本体上形成包含锗的包覆层，并使通道体退火， 锗扩散到通道体内。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20140027860A1
公开(公告)日：2014-01-30
申请号：US13560513
申请日：2012-07-27
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L29/1054
摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
摘要翻译： 公开了用于定制鳍式晶体管器件以提供同一集成电路管芯内的不同范围的通道配置和/或材料系统的技术。 根据一个示例性实施例，除去牺牲翅片并用适合于给定应用的任意组合和应变的定制半导体材料代替。 在一种这样的情况下，第一组牺牲翅片中的每一个凹陷或以其它方式移除并用p型材料代替，并且第二组牺牲翅片中的每一个凹入或以其它方式移除并且用n型 材料。 p型材料可以完全独立于n型材料的工艺，反之亦然。 使用本文提供的技术可实现许多其它电路配置和设备变化。
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公开(公告)号：US08957476B2
公开(公告)日：2015-02-17
申请号：US13722801
申请日：2012-12-20
IPC分类号： H01L21/8234 , H01L27/088
CPC分类号： H01L29/16 , H01L21/823431 , H01L27/0886 , H01L29/0669 , H01L29/1033 , H01L29/785 , H01L29/7853
摘要： Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.
摘要翻译： 本公开的实施例提供了与从硅（Si）到硅锗（SiGe）的薄晶体管元件的转换相关联的技术和配置。 在一个实施例中，一种方法包括提供具有设置在半导体衬底上的晶体管器件的沟道体的半导体衬底，沟道体包括硅，在沟道本体上形成包含锗的包覆层，并使通道体退火， 锗扩散到通道体内。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US20140027816A1
公开(公告)日：2014-01-30
申请号：US13560474
申请日：2012-07-27
申请人： Stephen M. Cea , Anand S. Murthy , Glenn A. Glass , Daniel B. Aubertine , Tahir Ghani , Jack T. Kavalieros , Roza Kotlyar
发明人： Stephen M. Cea , Anand S. Murthy , Glenn A. Glass , Daniel B. Aubertine , Tahir Ghani , Jack T. Kavalieros , Roza Kotlyar
IPC分类号： H01L29/78 , H01L29/165
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/06 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
摘要翻译： 公开了用于将高迁移率应变通道结合到鳍状晶体管（例如，诸如双栅极，三相等等的FinFET）中的技术，其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中，硅锗（SiGe）被包覆到硅散热片上以提供期望的应力，尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下，来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下，可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中，硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。
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9.发明授权公开(公告)号：US07833883B2
公开(公告)日：2010-11-16
申请号：US11692782
申请日：2007-03-28
CPC分类号： H01L29/7834 , C30B25/02 , C30B29/06 , H01L21/02381 , H01L21/02387 , H01L21/0243 , H01L21/02529 , H01L21/0262 , H01L21/02639 , H01L21/02658 , H01L29/66636 , H01L29/7848
摘要： A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped silicon film is also described. In the method, a substrate having a high polarity dielectric region and a low polarity crystalline region is provided. A precursor gas is flowed to provide a silyl surface above the high polarity dielectric region and a carbon-doped silicon layer above the low polarity crystalline region. The silyl surface is then removed from above the high polarity dielectric region. The flowing and removing steps are repeated to provide a carbon-doped silicon film of a desired thickness above the low polarity crystalline region.
摘要翻译： 描述了用于沉积外延碳掺杂硅膜的前体气体混合物。 前体气体混合物由体积的硅前体气体，一定体积的乙炔气体和一定体积的载气构成。 还描述了形成具有外延碳掺杂硅膜的半导体结构的方法。 在该方法中，提供具有高极性电介质区域和低极性结晶区域的衬底。 流动前体气体以在高极性电介质区域上方提供甲硅烷基表面，以及在低极性结晶区域上方的碳掺杂硅层。 然后从高极性介电区域上方除去甲硅烷基表面。 重复流动和去除步骤以提供在低极性结晶区域之上所需厚度的碳掺杂硅膜。
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10.发明申请公开(公告)号：US20080242061A1
公开(公告)日：2008-10-02
申请号：US11692782
申请日：2007-03-28
CPC分类号： H01L29/7834 , C30B25/02 , C30B29/06 , H01L21/02381 , H01L21/02387 , H01L21/0243 , H01L21/02529 , H01L21/0262 , H01L21/02639 , H01L21/02658 , H01L29/66636 , H01L29/7848
摘要： A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped silicon film is also described. In the method, a substrate having a high polarity dielectric region and a low polarity crystalline region is provided. A precursor gas is flowed to provide a silyl surface above the high polarity dielectric region and a carbon-doped silicon layer above the low polarity crystalline region. The silyl surface is then removed from above the high polarity dielectric region. The flowing and removing steps are repeated to provide a carbon-doped silicon film of a desired thickness above the low polarity crystalline region.
摘要翻译： 描述了用于沉积外延碳掺杂硅膜的前体气体混合物。 前体气体混合物由体积的硅前体气体，一定体积的乙炔气体和一定体积的载气构成。 还描述了形成具有外延碳掺杂硅膜的半导体结构的方法。 在该方法中，提供具有高极性电介质区域和低极性结晶区域的衬底。 流动前体气体以在高极性电介质区域上方提供甲硅烷基表面，以及在低极性结晶区域上方的碳掺杂硅层。 然后从高极性介电区域上方除去甲硅烷基表面。 重复流动和去除步骤以提供在低极性结晶区域之上所需厚度的碳掺杂硅膜。
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