STACKED EDGE COUPLERS IN THE BACK-END-OF-LINE STACK OF A PHOTONIC CHIP

    公开(公告)号:US20230314708A1

    公开(公告)日:2023-10-05

    申请号:US17658092

    申请日:2022-04-05

    Inventor: YUSHENG BIAN

    Abstract: A stacked edge coupler for a photonic chip is provided. The stacked edge coupler includes an insulating layer, a waveguide core, a first assisting waveguide, and a back-end-of-line stack. The first assisting waveguide is on the insulating layer. The waveguide core is over the first assisting waveguide and includes a tapered section. The back-end-of-line stack is over the waveguide core. The back-end-of-line stack includes a side edge, a dielectric layer, and a second assisting waveguide. The second assisting waveguide is on the dielectric layer and arranged adjacent to the side edge. The second assisting waveguide has an overlapping arrangement with the tapered section of the waveguide core.

    PHOTODETECTORS AND SEMICONDUCTOR DEVICES

    公开(公告)号:US20210265513A1

    公开(公告)日:2021-08-26

    申请号:US16798417

    申请日:2020-02-23

    Abstract: The present disclosure generally relates to structures for use in optoelectronic/photonic applications and integrated circuit (IC) chips. The present disclosure also relates to semiconductor devices having a photodetector coupled with a waveguide, more particularly, a photodetector with a butt-end coupled waveguide. The present disclosure provides a structure having a substrate, a photodetector arranged above the substrate, the photodetector having a core body and a coupler that is adjacent to the core body, in which the core body is configured to absorb light received by the coupler, and the coupler including a plurality of grating structures having respective widths that vary as a function of position relative to the core body.

    CLADDING STRUCTURE IN THE BACK END OF LINE OF PHOTONICS CHIPS

    公开(公告)号:US20230393340A1

    公开(公告)日:2023-12-07

    申请号:US17805686

    申请日:2022-06-06

    CPC classification number: G02B6/30 G02B6/132

    Abstract: IC chips for photonics applications are disclosed. An example IC chip includes a substrate, an optical component above the substrate, and a first connection level above the substrate. The first connection level includes the optical component and a first cladding structure, in which the optical component is covered by the first cladding structure. The IC chip also includes a second connection level on the first connection level. The second connection level includes a first interlayer dielectric material. The IC chip further includes a second cladding structure directly above the optical component. The second cladding structure has at least a section within the second connection level. The second cladding structure is on the first cladding structure. The second cladding structure is laterally adjacent to and in direct contact with the first interlayer dielectric material. The second cladding structure includes a material different from the first interlayer dielectric material.

    PHOTONIC DEVICES INTEGRATED WITH REFLECTORS

    公开(公告)号:US20220057576A1

    公开(公告)日:2022-02-24

    申请号:US17454063

    申请日:2021-11-09

    Abstract: The present disclosure generally relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to semiconductor devices having a reflector and a photonic component and a method of forming the same. The present disclosure provides a semiconductor device having a substrate, a photonic component arranged above the substrate, a bottom reflector arranged above the substrate and positioned below the photonic component, in which the bottom reflector has a plurality of grating structures configured to reflect electromagnetic waves towards the photonic component, and a top reflector arranged above the photonic component, in which the top reflector has a plurality of grating structures configured to reflect electromagnetic waves towards the photonic component.

    EDGE COUPLERS IN THE BACK-END-OF-LINE STACK OF A PHOTONIC CHIP HAVING A SEALED CAVITY

    公开(公告)号:US20230324618A1

    公开(公告)日:2023-10-12

    申请号:US17658821

    申请日:2022-04-11

    Inventor: YUSHENG BIAN

    CPC classification number: G02B6/305 G02B6/1225 G02B6/1228 G02B6/136

    Abstract: According to an aspect of the present disclosure, an edge coupler for a photonic chip is provided. The edge coupler includes a substrate having a top surface, a sealed cavity in the substrate, a waveguide core, and a back-end-of-line stack. The sealed cavity has varying depths relative to the top surface of the substrate. The waveguide core is over the sealed cavity. The back-end-of-line stack includes a side edge, an interlayer dielectric layer, and an assisting waveguide. The assisting waveguide is on the interlayer dielectric layer adjacent to the side edge. The assisting waveguide and the waveguide core have an overlapping arrangement with the sealed cavity in the substrate.

    PHOTONIC DEVICES INTEGRATED WITH REFLECTORS

    公开(公告)号:US20210286130A1

    公开(公告)日:2021-09-16

    申请号:US16817582

    申请日:2020-03-12

    Abstract: The present disclosure generally relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to semiconductor devices having a reflector and a photonic component and a method of forming the same. The present disclosure provides a semiconductor device having a substrate, a photonic component arranged above the substrate, a bottom reflector arranged above the substrate and positioned below the photonic component, in which the bottom reflector has a plurality of grating structures configured to reflect electromagnetic waves towards the photonic component, and a top reflector arranged above the photonic component, in which the top reflector has a plurality of grating structures configured to reflect electromagnetic waves towards the photonic component.

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