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1.发明授权公开(公告)号：US07285819B2
公开(公告)日：2007-10-23
申请号：US11188582
申请日：2005-07-25
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/4232 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7923
摘要： An array of storage cells include a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
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公开(公告)号：US20070020820A1
公开(公告)日：2007-01-25
申请号：US11188909
申请日：2005-07-25
IPC分类号： H01L21/8232
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/7885 , Y10S977/707 , Y10S977/712
摘要： A process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and forming a trench within the substrate. The process can also include forming a second set of discontinuous storage elements within the trench. The process can further include forming a first gate electrode within the trench, wherein a discontinuous storage element lies between the first gate electrode and a wall of the trench. The process can still further include removing a part of the second set of discontinuous storage elements and forming a second gate electrode over the first gate electrode. After forming the second gate electrode, substantially none of the second set of discontinuous storage elements lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and the primary surface of the substrate.
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公开(公告)号：US20070018240A1
公开(公告)日：2007-01-25
申请号：US11188910
申请日：2005-07-25
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , B82Y10/00 , G11C16/0475 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825 , Y10S977/707 , Y10S977/712
摘要： An electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a first set of discontinuous storage elements that overlie a primary surface of the substrate and a second set of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein substantially none of the discontinuous storage elements lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and the primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
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公开(公告)号：US07582929B2
公开(公告)日：2009-09-01
申请号：US11188999
申请日：2005-07-25
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译： 电子设备可以包括位于沟槽内的不连续存储元件。 在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。 电子设备还可以包括位于沟槽内的不连续存储元件的一部分。 电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。 电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。 在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。
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公开(公告)号：US07205608B2
公开(公告)日：2007-04-17
申请号：US11188910
申请日：2005-07-25
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7887 , B82Y10/00 , G11C16/0475 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825 , Y10S977/707 , Y10S977/712
摘要： An electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a first set of discontinuous storage elements that overlie a primary surface of the substrate and a second set of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein substantially none of the discontinuous storage elements lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and the primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译： 电子设备可以包括具有包括壁和底部的沟槽的衬底。 电子设备还可以包括覆盖在衬底的主表面上的第一组不连续存储元件和位于沟槽内的第二组不连续存储元件。 电子器件还可以包括第一栅电极，其中在第一栅电极和衬底的主表面之间的上表面和第一栅极电极的上表面之间基本上不存在不连续的存储元件沿着沟槽的壁。 电子器件还可以包括覆盖第一栅电极和主表面的第二栅电极。 在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。
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6.发明授权Process for forming an electronic device including discontinuous storage elements 失效用于形成包括不连续存储元件的电子设备的方法公开(公告)号：US07619275B2
公开(公告)日：2009-11-17
申请号：US11188935
申请日：2005-07-25
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译： 用于形成电子器件的方法可以包括在衬底内形成沟槽，其中沟槽包括壁和底部。 该方法还可以包括形成位于沟槽内的不连续存储元件的一部分，以及在形成不连续存储元件之后在沟槽内形成第一栅电极。 至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。 该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。
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7.发明授权Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming 有权使用热载流子注入编程的连续控制栅极制造非易失性存储阵列的方法公开(公告)号：US07314798B2
公开(公告)日：2008-01-01
申请号：US11188583
申请日：2005-07-25
IPC分类号： H01L21/336
CPC分类号： H01L29/7887 , B82Y10/00 , H01L27/115 , H01L27/11519 , H01L27/11556 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/7923 , H01L29/7926
摘要： A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the trenches where the charge storage stack includes a layer of discontinuous storage elements (DSEs). A control gate overlies the first trench. The control gate may run perpendicular to the trenches and traverse the first and second trenches. In another implementation, the control gate runs parallel with the trenches. The storage cell may include one or more diffusion regions occupying an upper surface of the substrate between the first and second trenches. The diffusion region may reside between first and second control gates that are parallel to the trenches. Alternatively, a pair of diffusion regions may occur on either side of a control gate that is perpendicular to the trenches.
摘要翻译： 制造存储单元阵列的方法包括在半导体衬底中限定的第一沟槽下面的第一源极/漏极区域和在衬底中的第二沟槽下面的第二源极/漏极区域。 电荷存储堆叠线路中的每个沟槽，其中电荷存储堆叠包括不连续存储元件（DSE）层。 控制门覆盖在第一沟槽上。 控制栅极可以垂直于沟槽延伸并穿过第一和第二沟槽。 在另一实现中，控制栅极与沟槽平行地延伸。 存储单元可以包括占据第一和第二沟槽之间的衬底的上表面的一个或多个扩散区域。 扩散区域可以驻留在平行于沟槽的第一和第二控制栅极之间。 或者，一对扩散区域可以发生在垂直于沟槽的控制栅极的任一侧上。
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8.发明授权Process for forming an electronic device including discontinuous storage elements 有权用于形成包括不连续存储元件的电子设备的方法公开(公告)号：US07226840B2
公开(公告)日：2007-06-05
申请号：US11188909
申请日：2005-07-25
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/7885 , Y10S977/707 , Y10S977/712
摘要： A process for forming an electronic device can include forming a first set of discontinuous storage elements over a primary surface of a substrate and forming a trench within the substrate. The process can also include forming a second set of discontinuous storage elements within the trench. The process can further include forming a first gate electrode within the trench, wherein a discontinuous storage element lies between the first gate electrode and a wall of the trench. The process can still further include removing a part of the second set of discontinuous storage elements and forming a second gate electrode over the first gate electrode. After forming the second gate electrode, substantially none of the second set of discontinuous storage elements lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and the primary surface of the substrate.
摘要翻译： 用于形成电子器件的工艺可以包括在衬底的主表面上形成第一组不连续存储元件，并在衬底内形成沟槽。 该工艺还可以包括在沟槽内形成第二组不连续的存储元件。 该工艺还可以包括在沟槽内形成第一栅电极，其中不连续存储元件位于第一栅电极和沟槽的壁之间。 该方法还可以进一步包括去除第二组不连续存储元件的一部分并在第一栅电极上形成第二栅电极。 在形成第二栅极电极之后，在第一栅电极的上表面和基板的主表面之间的高度处，基本上没有第二组不连续存储元件不沿着沟槽的壁放置。
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9.发明授权Programming and erasing structure for a floating gate memory cell and method of making 有权浮动存储单元的编程和擦除结构及其制作方法公开(公告)号：US07745870B2
公开(公告)日：2010-06-29
申请号：US11626681
申请日：2007-01-24
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.
摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。 蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。 控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。 浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。 该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。 电子能够容易地在两层之间移动。 因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。
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10.发明授权Method of fabricating a storage device including decontinuous storage elements within and between trenches 有权制造包括槽内和沟槽之间的不连续存储元件的存储装置的方法公开(公告)号：US07592224B2
公开(公告)日：2009-09-22
申请号：US11393287
申请日：2006-03-30
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0458 , G11C2216/06 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.
摘要翻译： 半导体存储单元包括在半导体层中限定的第一沟槽下面的第一源极/漏极区域。 第二源极/漏极区域位于半导体层中的第二沟槽的下方。 第一沟槽中的第一选择栅极和第二沟槽中的第二选择栅极由选择栅极电介质排列。 电荷存储堆叠覆盖选择栅极，并且控制栅极覆盖堆叠。 DSE可以包括多晶硅的谨慎积累。 第一和第二选择栅极的上表面比第一和第二沟槽的上表面低。 控制栅极可以是垂直于选择栅极横穿并行进的连续控制栅极。 电池可以包括到半导体层的触点。 控制栅极可以包括覆盖第一选择栅极的第一控制栅极和覆盖第二选择栅极的第二控制栅极。
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