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1.发明授权Method of fabricating a storage device including decontinuous storage elements within and between trenches 有权制造包括槽内和沟槽之间的不连续存储元件的存储装置的方法公开(公告)号：US07592224B2
公开(公告)日：2009-09-22
申请号：US11393287
申请日：2006-03-30
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0458 , G11C2216/06 , H01L27/11521 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： A semiconductor storage cell includes a first source/drain region underlying a first trench defined in a semiconductor layer. A second source/drain region underlies a second trench in the semiconductor layer. A first select gate in the first trench and a second select gate in the second trench are lined by a select gate dielectric. A charge storage stack overlies the select gates and a control gate overlies the stack. The DSEs may comprise discreet accumulations of polysilicon. An upper surface of the first and second select gates is lower than an upper surface of the first and second trenches. The control gate may be a continuous control gate traversing and running perpendicular to the select gates. The cell may include contacts to the semiconductor layer. The control gate may include a first control gate overlying the first select gate and a second control gate overlying the second select gate.
摘要翻译： 半导体存储单元包括在半导体层中限定的第一沟槽下面的第一源极/漏极区域。 第二源极/漏极区域位于半导体层中的第二沟槽的下方。 第一沟槽中的第一选择栅极和第二沟槽中的第二选择栅极由选择栅极电介质排列。 电荷存储堆叠覆盖选择栅极，并且控制栅极覆盖堆叠。 DSE可以包括多晶硅的谨慎积累。 第一和第二选择栅极的上表面比第一和第二沟槽的上表面低。 控制栅极可以是垂直于选择栅极横穿并行进的连续控制栅极。 电池可以包括到半导体层的触点。 控制栅极可以包括覆盖第一选择栅极的第一控制栅极和覆盖第二选择栅极的第二控制栅极。
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公开(公告)号：US06887758B2
公开(公告)日：2005-05-03
申请号：US10267153
申请日：2002-10-09
IPC分类号： H01L21/336 , H01L29/792 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/66833 , H01L29/792
摘要： A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source (52) and drain (54) having a second conductivity type are implanted into the substrate (20). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region (46) on the drain side allows a higher programming speed, and the highly doped layer (26) allows the use of a short channel device.
摘要翻译： 半导体器件（10）具有均匀地注入到半导体衬底（20）中的具有第一导电类型的高掺杂层（26）。 氧化物 - 氧化物 - 氧化物结构（36,38,40）形成在半导体衬底（20）上。 具有第一导电类型的卤素区域（46）以仅在氧化物 - 氧化物 - 氧化物结构的漏极侧的角度被注入，并且在氧化物 - 氮化物 - 氧化物结构之下延伸到氧化氮化物 - 氮化物的边缘的预定距离 氧化物结构。 具有第二导电类型的源极（52）和漏极（54）被注入衬底（20）中。 所得的非易失性存储单元提供低的自然阈值电压，以在读周期期间最小化阈值电压漂移。 此外，在漏极侧使用卤素区域（46）允许更高的编程速度，并且高掺杂层（26）允许使用短通道器件。
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3.发明授权公开(公告)号：US06713812B1
公开(公告)日：2004-03-30
申请号：US10267199
申请日：2002-10-09
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L27/11521 , H01L29/105 , H01L29/66833 , H01L29/792
摘要： A memory device (70) that uses a non-volatile storage element (38), such as nitride, has reduced read disturb, which is the problem of tending to increase the threshold voltage of a memory device (70) during a read. To reduce this effect, the memory device (70) uses a counterdoped channel (86) to lower the natural threshold voltage of the device (70). This counterdoping can even be of sufficient dosage to reverse the conductivity type of the channel (86) and causing a negative natural threshold voltage. This allows for a lower gate voltage during read to reduce the adverse effect of performing a read. An anti-punch through (ATP) region (74) below the channel (86) allows for the lightly doped or reversed conductivity type channel (86) to avoid short channel leakage. A halo implant (46) on the drain side (54, 53) assists in hot carrier injection (HCI) so that the HCI is effective even though the channel (86) is lightly doped or of reversed conductivity type.
摘要翻译： 使用诸如氮化物的非易失性存储元件（38）的存储器件（70）具有减少的读取干扰，这是读取期间倾向于增加存储器件（70）的阈值电压的问题。 为了减少这种影响，存储装置（70）使用反向通道（86）来降低装置（70）的自然阈值电压。 这种反渗透甚至可以具有足够的剂量来反转通道（86）的导电类型并导致负的自然阈值电压。 这在读取期间允许较低的栅极电压以减少执行读取的不利影响。 在沟道（86）下方的抗穿透（ATP）区域（74）允许轻掺杂或反向导电型通道（86）避免短沟道泄漏。 漏极侧（54,53）上的卤素注入（46）有助于热载流子注入（HCI），使得尽管通道（86）被轻掺杂或反向导电类型，HCI也是有效的。
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公开(公告)号：US07619270B2
公开(公告)日：2009-11-17
申请号：US11188591
申请日：2005-07-25
IPC分类号： H01L29/72
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0433 , G11C16/0458 , G11C16/0475 , G11C16/0491 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： An electronic device can include discontinuous storage elements that lie within a trench. The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate. The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译： 电子设备可以包括位于沟槽内的不连续存储元件。 电子器件可以包括包括沟槽的衬底，其包括壁和底部并且从衬底的主表面延伸。 电子设备还可以包括不连续的存储元件，其中不连续存储元件的一部分至少位于沟槽内。 电子器件还可以包括第一栅极电极，其中不连续存储元件的部分的至少一部分位于第一栅电极和沟槽的壁之间。 电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。
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公开(公告)号：US20070020857A1
公开(公告)日：2007-01-25
申请号：US11188939
申请日：2005-07-25
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/7624 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42348 , H01L29/42352 , Y10S977/707
摘要： A process for forming an electronic device can include forming a first trench within a substrate, wherein the trench includes a wall and a bottom and extends from a primary surface of the substrate. The process can also include forming discontinuous storage elements and forming a first gate electrode within the trench such that, a first discontinuous storage element of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The process can further include removing the discontinuous storage elements that overlie the primary surface of the substrate. The process can still further include forming a second gate electrode that overlies the first gate electrode and the primary surface of the substrate.
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6.发明授权Back-gated semiconductor device with a storage layer and methods for forming thereof 有权具有存储层的后门控半导体器件及其形成方法公开(公告)号：US07679125B2
公开(公告)日：2010-03-16
申请号：US11300077
申请日：2005-12-14
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L21/84 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.
摘要翻译： 制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体衬底，存储层和栅极材料层。 存储层可以位于半导体结构和栅极材料层之间，并且存储层可以比半导体结构更靠近第二晶片的第一侧。 该方法还包括将第二晶片的第一侧布置到第一晶片。 该方法还包括去除半导体结构的第一部分以在结合之后留下半导体结构层。 该方法还包括形成具有沟道区的晶体管，其中沟道区的至少一部分由半导体结构的层形成。
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公开(公告)号：US07582929B2
公开(公告)日：2009-09-01
申请号：US11188999
申请日：2005-07-25
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译： 电子设备可以包括位于沟槽内的不连续存储元件。 在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。 电子设备还可以包括位于沟槽内的不连续存储元件的一部分。 电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。 电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。 在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。
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公开(公告)号：US07205608B2
公开(公告)日：2007-04-17
申请号：US11188910
申请日：2005-07-25
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7887 , B82Y10/00 , G11C16/0475 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825 , Y10S977/707 , Y10S977/712
摘要： An electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a first set of discontinuous storage elements that overlie a primary surface of the substrate and a second set of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein substantially none of the discontinuous storage elements lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and the primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译： 电子设备可以包括具有包括壁和底部的沟槽的衬底。 电子设备还可以包括覆盖在衬底的主表面上的第一组不连续存储元件和位于沟槽内的第二组不连续存储元件。 电子器件还可以包括第一栅电极，其中在第一栅电极和衬底的主表面之间的上表面和第一栅极电极的上表面之间基本上不存在不连续的存储元件沿着沟槽的壁。 电子器件还可以包括覆盖第一栅电极和主表面的第二栅电极。 在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。
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9.发明授权Programming and erasing structure for a floating gate memory cell and method of making 有权浮动存储单元的编程和擦除结构及其制作方法公开(公告)号：US07094645B2
公开(公告)日：2006-08-22
申请号：US10944239
申请日：2004-09-17
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two adjacent floating gate layers. The top layer is made to have a contour while leaving the lower layer substantially unchanged. An interlevel dielectric and a control gate follow the contour of the floating gate to increase capacitance between the control gate and the floating gate. The two layers of the floating gate can be polysilicon in which the top layer has the contour formed therein by use of a sacrificial layer. The sacrificial layer is formed over the bottom polysilicon layer and etched. The top polysilicon layer is formed over the sacrificial layer. Subsequent processing of the top polysilicon layer exposes the remaining portion of the sacrificial layer so it can be removed; leaving the contour in the top polysilicon layer for the interlevel dielectric and the control gate.
摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个相邻的浮置栅极层。 顶层制成具有轮廓，同时使下层基本上保持不变。 一个层间电介质和一个控制栅极跟随着浮栅的轮廓，以增加控制栅和浮栅之间的电容。 浮栅的两层可以是多晶硅，其中顶层具有通过使用牺牲层形成在其中的轮廓。 牺牲层形成在底部多晶硅层上并被蚀刻。 顶部多晶硅层形成在牺牲层上。 顶部多晶硅层的后续处理暴露了牺牲层的剩余部分，使得其可以被去除; 将轮廓留在层间电介质和控制栅极的顶部多晶硅层中。
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10.发明授权Programming and erasing structure for a floating gate memory cell and method of making 有权浮动存储单元的编程和擦除结构及其制作方法公开(公告)号：US07745870B2
公开(公告)日：2010-06-29
申请号：US11626681
申请日：2007-01-24
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.
摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。 蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。 控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。 浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。 该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。 电子能够容易地在两层之间移动。 因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。
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