公开(公告)号：US20080204103A1

公开(公告)日：2008-08-28

申请号：US12071635

申请日：2008-02-25

申请人： Gun-Ok Jung ,  Chung-Hee Kim

发明人： Gun-Ok Jung ,  Chung-Hee Kim

IPC分类号： H03H11/26 ,  G06F1/04

CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K5/15013

摘要： A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal

摘要翻译： 用于调整输入到第一时钟网格的第一时钟与第二时钟网格的第二时钟网格输入之间的偏斜的时钟偏移控制器包括脉冲发生器，其适于输出对应于延迟时间之间的脉冲信号 从第一时钟网格输出的第一输出时钟和从第二时钟网格输出的第二输出时钟，适于产生对应于脉冲信号的脉冲宽度的数字信号的脉冲宽度检测器，以及适于延迟的时钟延迟调整器 第一和第二时钟之一对应于数字信号

公开(公告)号：US07971088B2

公开(公告)日：2011-06-28

申请号：US12071635

申请日：2008-02-25

申请人： Gun-Ok Jung ,  Chung-Hee Kim

发明人： Gun-Ok Jung ,  Chung-Hee Kim

IPC分类号： G06F1/04

CPC分类号： G06F1/10 ,  H03K5/133 ,  H03K5/15013

摘要： A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal.

摘要翻译： 用于调整输入到第一时钟网格的第一时钟与第二时钟网格的第二时钟网格输入之间的偏斜的时钟偏移控制器包括脉冲发生器，其适于输出对应于延迟时间之间的脉冲信号 从第一时钟网格输出的第一输出时钟和从第二时钟网格输出的第二输出时钟，适于产生对应于脉冲信号的脉冲宽度的数字信号的脉冲宽度检测器，以及适于延迟的时钟延迟调整器 第一和第二时钟之一对应于数字信号。

公开(公告)号：US07623406B2

公开(公告)日：2009-11-24

申请号：US11705485

申请日：2007-02-12

申请人： Gi-Ho Park ,  Gun-Ok Jung

发明人： Gi-Ho Park ,  Gun-Ok Jung

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C11/413 ,  G11C16/08

摘要： A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells according to the word line voltage and additional access information separate from the address.

摘要翻译： 半导体存储器件包括存储单元阵列，解码器和访问控制单元。 解码器根据存储单元阵列中的多个存储单元的地址产生字线电压。 访问控制单元根据字线电压和与该地址分离的附加访问信息控制对多个存储器单元的访问。

公开(公告)号：US08542033B2

公开(公告)日：2013-09-24

申请号：US13234811

申请日：2011-09-16

申请人： Hyoung-Wook Lee ,  Gun-Ok Jung ,  Suhwan Kim ,  Ah-Reum Kim ,  Rahul Singh

发明人： Hyoung-Wook Lee ,  Gun-Ok Jung ,  Suhwan Kim ,  Ah-Reum Kim ,  Rahul Singh

IPC分类号： H03K19/00

CPC分类号： H03K19/0966

摘要： A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first phase of a clock signal, and evaluates a plurality of input signals to determine a logic level of the first dynamic node in a second phase of the clock signal. The second evaluation unit precharges a second dynamic node in the first phase of the clock signal, and determines a logic level of the second dynamic node in response to a logic level of the footer node in the second phase of the clock signal. The output unit provides an output signal having a logic level according to levels of a first voltage of the first dynamic node and a second voltage of the second dynamic node.

摘要翻译： 多米诺逻辑电路包括第一评估单元，第二评估单元和输出单元。 第一评估单元对第一动态节点进行预充电，在时钟信号的第一阶段放电页脚节点，并且评估多个输入信号以在时钟信号的第二阶段中确定第一动态节点的逻辑电平。 第二评估单元在时钟信号的第一阶段中对第二动态节点进行预充电，并且响应于时钟信号的第二阶段中的页脚节点的逻辑电平来确定第二动态节点的逻辑电平。 输出单元提供具有根据第一动态节点的第一电压的电平和第二动态节点的第二电压的逻辑电平的输出信号。

公开(公告)号：US20070195598A1

公开(公告)日：2007-08-23

申请号：US11705485

申请日：2007-02-12

申请人： Gi-Ho Park ,  Gun-Ok Jung

发明人： Gi-Ho Park ,  Gun-Ok Jung

IPC分类号： G11C16/04 ,  G11C5/14 ,  G11C8/00 ,  G11C11/34 ,  G11C7/02

CPC分类号： G11C8/10 ,  G11C11/413 ,  G11C16/08

摘要： A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells according to the word line voltage and additional access information separate from the address.

摘要翻译： 半导体存储器件包括存储单元阵列，解码器和访问控制单元。 解码器根据存储单元阵列中的多个存储单元的地址产生字线电压。 访问控制单元根据字线电压和与该地址分离的附加访问信息控制对多个存储器单元的访问。

公开(公告)号：US07348837B2

公开(公告)日：2008-03-25

申请号：US11297004

申请日：2005-12-08

申请人： Gun-Ok Jung ,  Young-Min Shin

发明人： Gun-Ok Jung ,  Young-Min Shin

IPC分类号： H01L25/00

CPC分类号： G06F1/10

摘要： For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.

摘要翻译： 为了将信号分配到区域中的负载，该区域被分成多个区域。 相应的信号点设置在每个区域中，用于向该区域中的负载提供信号。 相应的扩散点设置在任何两个相邻信号点之间。 信号最初被施加到信号和扩散点的中心点。 在给定信号或扩散点处接收到的信号被传送到与给定信号或扩散点的最大距离内的任何信号或扩散点。

公开(公告)号：US20050052211A1

公开(公告)日：2005-03-10

申请号：US10910644

申请日：2004-08-04

申请人： Gun-Ok Jung ,  Jin-Han Kim ,  Sung-Bae Park ,  Chul-Woo Kim ,  Seok-Soo Yoon ,  Seok-Ryoung Yoon

发明人： Gun-Ok Jung ,  Jin-Han Kim ,  Sung-Bae Park ,  Chul-Woo Kim ,  Seok-Soo Yoon ,  Seok-Ryoung Yoon

IPC分类号： G06F1/06 ,  H03H11/26 ,  H03K5/00 ,  H03K5/05 ,  H03K5/13 ,  H03K5/135 ,  H03K5/15 ,  H03K5/26 ,  H03L7/081 ,  H04L7/02

CPC分类号： H03K5/133 ,  H03K5/135 ,  H03K2005/00156 ,  H03K2005/00286

摘要： A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (π), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.

摘要翻译： 一种可以被配置为通过指定的相位差产生延迟的时钟信号的装置，其可以包括用于产生至少一个时钟信号的时钟发生器电路，用于延迟所述至少一个时钟信号的延迟时钟信号发生器，相位检测电路 用于基于根据半周期（pi）检测到的相位延迟量来生成选择信号，并且与时钟信号相比，相位插值电路用于控制延迟的时钟信号的延迟时间并内插延迟的时钟 信号，以及输出延迟了指定相位差的延迟时钟信号的选择电路。

公开(公告)号：US07944267B2

公开(公告)日：2011-05-17

申请号：US12752389

申请日：2010-04-01

申请人： Gun-Ok Jung

发明人： Gun-Ok Jung

IPC分类号： H03K17/687

CPC分类号： G01R31/275 ,  G01R31/2621 ,  G01R31/3008 ,  H03K2217/0036

摘要： A leakage current measurement circuit measuring a substrate leakage current and a gate leakage current in response to a variation in the size of an MOS transistor and a leakage current comparison circuit judging which one of the substrate leakage current and the gate leakage current is dominant. The leakage current measurement circuit includes a charge supply, a leakage current generator and a detection signal generator. The leakage current comparison circuit includes a charge supply, a leakage current comparator and a detection signal generator.

摘要翻译： 泄漏电流测量电路，其响应于MOS晶体管和泄漏电流比较电路的尺寸变化来测量衬底漏电流和栅极漏电流，判断衬底泄漏电流和栅极漏电流中哪一个占优势。 泄漏电流测量电路包括电荷源，漏电流发生器和检测信号发生器。 泄漏电流比较电路包括电荷源，漏电流比较器和检测信号发生器。

公开(公告)号：US07180340B2

公开(公告)日：2007-02-20

申请号：US10655024

申请日：2003-09-05

申请人： Gun-Ok Jung ,  Sung-Bae Park

发明人： Gun-Ok Jung ,  Sung-Bae Park

IPC分类号： H03B19/00

CPC分类号： H03K5/00006 ,  G06F7/68 ,  H03K5/1565 ,  H03L7/0814

摘要： Provided is a frequency multiplier including a delay circuit, an XOR gate, and a control circuit and a method of operating such a frequency multiplier to adjust the duty cycle of a clock signal. During operation of the frequency multiplier the delay circuit receives a first clock signal and generates a delayed clock signal. The XOR gate receives the first clock signal and the delayed clock signal, performs an XOR operation on the received signals and outputs a second clock signal that has a frequency that is a multiple of the first clock signal. The control circuit monitors the phase difference between the first clock signal and the delayed clock signal and outputs a control signal corresponding to the detected phase difference to the delay circuit to adjust the time delay applied to the first clock signal by the delay circuit.

摘要翻译： 提供了包括延迟电路，异或门和控制电路的倍频器，以及操作这种倍频器以调整时钟信号的占空比的方法。 在倍频器的操作期间，延迟电路接收第一时钟信号并产生延迟的时钟信号。 异或门接收第一时钟信号和延迟的时钟信号，对接收的信号执行异或运算，并输出具有第一时钟信号倍数的频率的第二时钟信号。 控制电路监视第一时钟信号和延迟的时钟信号之间的相位差，并将对应于检测到的相位差的控制信号输出到延迟电路，以通过延迟电路调整施加到第一时钟信号的时间延迟。

公开(公告)号：US20060125542A1

公开(公告)日：2006-06-15

申请号：US11297004

申请日：2005-12-08

申请人： Gun-Ok Jung ,  Young-Min Shin

发明人： Gun-Ok Jung ,  Young-Min Shin

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： For distributing a signal to loads in an area, the area is divided into a plurality of regions. A respective signal point is disposed in each region for providing the signal to a load in the region. A respective diffusion point is disposed between any two neighboring signal points. The signal is initially applied to a center point of the signal and diffusion points. The signal when received at a given signal or diffusion point is transmitted to any of the signal or diffusion points within a maximum distance from the given signal or diffusion point.

摘要翻译： 为了将信号分配到区域中的负载，该区域被分成多个区域。 相应的信号点设置在每个区域中，用于向该区域中的负载提供信号。 相应的扩散点设置在任何两个相邻信号点之间。 信号最初被施加到信号和扩散点的中心点。 在给定信号或扩散点处接收到的信号被传送到与给定信号或扩散点的最大距离内的任何信号或扩散点。