公开(公告)号：US6049136A

公开(公告)日：2000-04-11

申请号：US89684

申请日：1998-06-03

申请人： Guy H. Humphrey ,  Rory L. Fisher ,  Jerry D'Amato

发明人： Guy H. Humphrey ,  Rory L. Fisher ,  Jerry D'Amato

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L21/822 ,  H01L23/485 ,  H01L23/50 ,  H01L23/66 ,  H01L27/04 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/02 ,  H01L23/50 ,  H01L23/66 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043

摘要： The present invention is generally directed to a an integrated circuit package having a unique lead configuration, wherein the integrated circuit package is constructed from a die containing an integrated circuit. The die has a plurality of leads for carrying electrical signals to and from the integrated circuit, wherein the plurality of leads are disposed over a bottom side of the die. The package further includes a multi-layer substrate having at least two signal layers. The substrate is juxtaposed against the die and has a plurality of contacts disposed along a top side to align with the leads of the die to carry the electrical signals to conductive paths within the at least two signal layers. The multi-layer substrate has a larger adjoining surface area than the die and further has a plurality of leads disposed across a bottom side for connection with a printed circuit board, the on the bottom side being in communication with the leads of the top side by way of the conductive paths disposed within the substrate. The leads of the die are disposed such that at least two high speed rows of leads are disposed in parallel fashion near the center of the die, wherein the high speed rows are for carrying high frequency electrical signals. At least two sets of low speed rows of leads are disposed in parallel fashion near the sides of the die, and spaced apart from the high speed rows.

摘要翻译： 本发明一般涉及一种具有独特引线结构的集成电路封装，其中该集成电路封装由包含集成电路的管芯构成。 芯片具有多个用于将电信号传送到集成电路的引线，其中多个引线设置在模具的底侧之上。 该封装还包括具有至少两个信号层的多层基板。 衬底与裸片并置并且具有沿着顶侧布置的多个触点，以与芯片的引线对准以将电信号传送到至少两个信号层内的导电路径。 多层基板具有比模具更大的邻接表面积，并且还具有跨越底侧设置用于与印刷电路板连接的多个引线，底部侧与顶侧的引线连通， 设置在基板内的导电路径的方式。 芯片的引线被设置成使得至少两个高速行的引线以平行的方式设置在芯片的中心附近，其中高速行用于承载高频电信号。 至少两组低速行的引线以平行方式设置在模具的侧面附近并且与高速行间隔开。

公开(公告)号：US6137849A

公开(公告)日：2000-10-24

申请号：US150059

申请日：1998-09-09

申请人： Guy H. Humphrey

发明人： Guy H. Humphrey

IPC分类号： H04L25/14 ,  H04L7/00

CPC分类号： H04L25/14

摘要： The present invention is generally directed to a method and apparatus for transferring data from an integrated circuit that is capable of bidirectional data communication. In accordance with one aspect of the invention, an apparatus is provided having a circuit for splitting the data into two portions--a high bit portion and a low bit portion. The circuit also includes two data paths. A first data path communicates the high bit portion of the data and a second data path communicates the low bit portion of the data. The apparatus further includes an output circuit that is configured to connect outputs of the first and second data paths to a common, bidirectional data bus. Finally the apparatus includes a hold circuit configured to hold a last data value on the common data bus for at least one clock cycle before allowing circuitry to receive data from the common bus. A method is also provided for transferring data from an integrated circuit capable of bidirectional data communication. The method operates by splitting data into a first group of bits and a second group of bits. The method further includes steps of transmitting the first group of bits along a first data path, and transmitting the second group of bits along a second data path. The method then electrically connects an output of the first data path to an output of the second data path at a common directional data bus, and alternatively transmits data over the first path and the second path. When alternating the data transmissions in this way, the method ensures that the two data path outputs are not driven at the same time. Finally, the method holds a last data value on the common bus for at least one clock cycle before receiving data over the common bus.

摘要翻译： 本发明一般涉及用于从能够进行双向数据通信的集成电路传送数据的方法和装置。 根据本发明的一个方面，提供一种装置，其具有用于将数据分成两部分的电路 - 高位部分和低位部分。 该电路还包括两条数据路径。 第一数据路径传送数据的高位部分，第二数据路径传送数据的低位部分。 该装置还包括输出电路，其被配置为将第一和第二数据路径的输出连接到公共的双向数据总线。 最后，该装置包括保持电路，其被配置为在允许电路从公共总线接收数据之前，将公共数据总线上的最后数据值保持至少一个时钟周期。 还提供了一种从能够进行双向数据通信的集成电路传送数据的方法。 该方法通过将数据分成第一组位和第二组位来操作。 该方法还包括以下步骤：沿第一数据路径发送第一组位，以及沿第二数据路径发送第二组位。 该方法然后在公共方向数据总线上将第一数据路径的输出电连接到第二数据路径的输出，或者在第一路径和第二路径上传输数据。 当以这种方式交换数据传输时，该方法确保两个数据路径输出不被同时驱动。 最后，该方法在通过公共总线接收数据之前，在公共总线上保持至少一个时钟周期的最后一个数据值。

公开(公告)号：US6118169A

公开(公告)日：2000-09-12

申请号：US204021

申请日：1998-12-01

申请人： Paul D Nuber ,  Dan Stotz ,  M. Jason Welch ,  Stephen E. Clarke ,  Guy H. Humphrey ,  C. Stephen Dondale

发明人： Paul D Nuber ,  Dan Stotz ,  M. Jason Welch ,  Stephen E. Clarke ,  Guy H. Humphrey ,  C. Stephen Dondale

IPC分类号： H01L27/04 ,  H01L21/77 ,  H01L21/822 ,  H01L27/118

CPC分类号： H01L27/118

摘要： A method for increasing the layer density uniformity across a conductive layer, which comprises a plurality of functional blocks, of an integrated circuit is presented. Increased uniformity is achieved by tiling a plurality of capacitors in between the functional blocks. The configuration of the capacitor array and number of the capacitor cells in the array is arranged so as to provide approximate uniformity in the conductor-to-non-conductor density across the entire conductive layer. The capacitor array may be used to reduce power supply switching noise by coupling one or more of the capacitor cells making up the capacitor array between a high power rail and a low power rail.

摘要翻译： 提出了一种用于增加集成电路的包括多个功能块的导电层之间的层密度均匀性的方法。 通过在功能块之间平铺多个电容器来实现均匀性的提高。 布置电容器阵列的配置和阵列中的电容器单元的数量，以便在整个导电层上提供导体与非导体密度的近似均匀性。 电容器阵列可以用于通过将构成电容器阵列的一个或多个电容器单元耦合在高功率轨道和低功率轨道之间来降低电源开关噪声。

公开(公告)号：US06400771B1

公开(公告)日：2002-06-04

申请号：US09119832

申请日：1998-07-21

申请人： Guy H. Humphrey

发明人： Guy H. Humphrey

IPC分类号： H04B300

CPC分类号： H04L25/028 ,  H04L25/0292

摘要： The present invention is generally directed to a driver circuit for a high speed transceiver. In accordance with one aspect of the invention, the driver circuit includes a first driver segment disposed to receive a control signal and configured to drive the control signal from a logic zero state to a logic one state and place the driven signal on a first driver segment output. Similarly, the driver circuit includes a second driver segment disposed to receive the control signal and configured to drive the control signal from a logic one state to a logic zero state and place the driven signal on a second driver segment output. In this regard, the control signal is a signal generated internally (i.e., within the chip) to be driven across a bus to another chip. The strength of the control signal must be increased before driving the control signal onto the bus. For this reason, the first driver segment and the second driver segment each include a plurality of drive units that are disposed in a cascaded configuration. As the control signal passes through each successive drive unit, it gains in signal strength. As will be appreciated by persons skilled in the art, this cascaded drive unit configuration provides for an extremely fast overall power build-up of the signals, as opposed to using a single, more powerful drive unit. To balance the timing delay between the two segments, a delay element is serially disposed within the segment have the fewer inversions.

摘要翻译： 本发明一般涉及用于高速收发器的驱动电路。 根据本发明的一个方面，驱动器电路包括第一驱动器段，其设置成接收控制信号并被配置为将控制信号从逻辑0状态驱动到逻辑1状态，并将驱动信号放置在第一驱动器段 输出。 类似地，驱动器电路包括设置成接收控制信号并被配置为将控制信号从逻辑1状态驱动到逻辑零状态并将驱动信号置于第二驱动器段输出上的第二驱动器段。 在这方面，控制信号是内部产生的信号（即，在芯片内部），要被驱动通过总线到另一个芯片。 在将控制信号驱动到总线上之前，必须增加控制信号的强度。 为此，第一驱动器段和第二驱动器段各自包括以级联配置布置的多个驱动单元。 当控制信号通过每个连续的驱动单元时，其信号强度增加。 如本领域技术人员将理解的，与使用单个更强大的驱动单元相反，该级联驱动单元配置提供了信号的极快的总体功率积分。 为了平衡两个段之间的定时延迟，在该段内串行设置的延迟元件具有较少的反转。

公开(公告)号：US6064224A

公开(公告)日：2000-05-16

申请号：US127775

申请日：1998-07-31

申请人： Gerald L. Esch, Jr. ,  Guy H. Humphrey

发明人： Gerald L. Esch, Jr. ,  Guy H. Humphrey

IPC分类号： G06F3/00 ,  H03K19/00 ,  H03K19/0175 ,  H03K17/16 ,  H03K19/003

CPC分类号： H03K19/0005

摘要： A circuit for matching the impedance of a first array of transistors to an external resistor is used to produce a first set of control signals. This first set of control signals is used to control another array of transistors to replicate the impedance of the first array of transistors. This replicated impedance is then used by another circuit for matching impedance to produce a second set of control signals that control an array of transistor of a different type to match the impedance of the first two array. The two sets of control signals may then be used as calibration signals for the pull-up and pull-down transistors of multiple output drivers.

摘要翻译： 用于将第一晶体管阵列的阻抗与外部电阻器匹配的电路用于产生第一组控制信号。 该第一组控制信号用于控制晶体管的另一阵列以复制第一晶体管阵列的阻抗。 然后，该复制阻抗被另一电路用于匹配阻抗以产生控制不同类型的晶体管阵列以匹配前两个阵列的阻抗的第二组控制信号。 然后可以将两组控制信号用作多个输出驱动器的上拉和下拉晶体管的校准信号。