公开(公告)号：US20140014904A1

公开(公告)日：2014-01-16

申请号：US13558532

申请日：2012-07-26

申请人： Guy M. Cohen ,  Michael A. Guillorn

发明人： Guy M. Cohen ,  Michael A. Guillorn

IPC分类号： H01L29/775 ,  B82Y99/00

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/413 ,  H01L29/42364 ,  H01L29/66439

摘要： In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.

摘要翻译： 一方面，提供一种FET器件。 FET器件包括衬底; 衬底上的半导体材料; 所述衬底上的至少一个栅极围绕用作所述器件的沟道区的所述半导体材料的一部分，其中从所述栅极延伸的所述半导体材料的部分用作所述器件的源极和漏极区域，并且其中所述源极和 器件的漏极区域从衬底移位; 覆盖栅极和半导体材料的器件上的平坦化电介质; 以及延伸穿过平坦化电介质并且围绕器件的源极和漏极区域的触点。

公开(公告)号：US08692229B2

公开(公告)日：2014-04-08

申请号：US13558532

申请日：2012-07-26

申请人： Guy M. Cohen ,  Michael A. Guillorn

发明人： Guy M. Cohen ,  Michael A. Guillorn

IPC分类号： H01L29/06 ,  H01L31/00

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/413 ,  H01L29/42364 ,  H01L29/66439

摘要： In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.

摘要翻译： 一方面，提供一种FET器件。 FET器件包括衬底; 衬底上的半导体材料; 所述衬底上的至少一个栅极围绕用作所述器件的沟道区的所述半导体材料的一部分，其中从所述栅极延伸的所述半导体材料的部分用作所述器件的源极和漏极区域，并且其中所述源极和 器件的漏极区域从衬底移位; 覆盖栅极和半导体材料的器件上的平坦化电介质; 以及延伸穿过平坦化电介质并且围绕器件的源极和漏极区域的触点。

公开(公告)号：US08642403B1

公开(公告)日：2014-02-04

申请号：US13547142

申请日：2012-07-12

申请人： Guy M. Cohen ,  Michael A. Guillorn

发明人： Guy M. Cohen ,  Michael A. Guillorn

IPC分类号： H01L21/335

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/413 ,  H01L29/42364 ,  H01L29/66439

摘要： In one aspect, a method of forming contacts to source and drain regions in a FET device includes the following steps. A patternable dielectric is deposited onto the device so as to surround each of the source and drain regions. The patternable dielectric is exposed to cross-link portions of the patternable dielectric that surround the source and drain regions. Uncross-linked portions of the patternable dielectric are selectively removed relative to the cross-linked portions of the patternable dielectric, wherein the cross-linked portions of the patternable dielectric form dummy contacts that surround the source and drain regions. A planarizing dielectric is deposited onto the device around the dummy contacts. The dummy contacts are selectively removed to form vias in the planarizing dielectric which are then filled with a metal(s) so as to form replacement contacts that surround the source and drain regions.

摘要翻译： 一方面，在FET器件中形成与源区和漏区的接触的方法包括以下步骤。 将可图形电介质沉积在器件上，以便围绕源极和漏极区域中的每一个。 可图形电介质暴露于围绕源极和漏极区域的可图案化电介质的交联部分。 可图形电介质的非交联部分相对于可图案化电介质的交联部分被选择性地去除，其中可图案电介质的交联部分形成围绕源区和漏区的虚拟接触。 平面化电介质沉积在虚拟触点周围的器件上。 虚拟触头被选择性地去除以在平坦化电介质中形成通孔，然后用金属填充以形成围绕源极和漏极区域的替换触点。

公开(公告)号：US20140017890A1

公开(公告)日：2014-01-16

申请号：US13547142

申请日：2012-07-12

申请人： Guy M. Cohen ,  Michael A. Guillorn

发明人： Guy M. Cohen ,  Michael A. Guillorn

IPC分类号： H01L21/768 ,  B82Y40/00

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/413 ,  H01L29/42364 ,  H01L29/66439

摘要： In one aspect, a method of forming contacts to source and drain regions in a FET device includes the following steps. A patternable dielectric is deposited onto the device so as to surround each of the source and drain regions. The patternable dielectric is exposed to cross-link portions of the patternable dielectric that surround the source and drain regions. Uncross-linked portions of the patternable dielectric are selectively removed relative to the cross-linked portions of the patternable dielectric, wherein the cross-linked portions of the patternable dielectric form dummy contacts that surround the source and drain regions. A planarizing dielectric is deposited onto the device around the dummy contacts. The dummy contacts are selectively removed to form vias in the planarizing dielectric which are then filled with a metal(s) so as to form replacement contacts that surround the source and drain regions.

摘要翻译： 一方面，在FET器件中形成与源区和漏区的接触的方法包括以下步骤。 将可图形电介质沉积在器件上，以便围绕源极和漏极区域中的每一个。 可图形电介质暴露于围绕源极和漏极区域的可图案化电介质的交联部分。 可图形电介质的非交联部分相对于可图案化电介质的交联部分被选择性地去除，其中可图案电介质的交联部分形成围绕源区和漏区的虚拟接触。 平面化电介质沉积在虚拟触点周围的器件上。 虚拟触头被选择性地去除以在平坦化电介质中形成通孔，然后用金属填充以形成围绕源极和漏极区域的替换触点。

公开(公告)号：US09368502B2

公开(公告)日：2016-06-14

申请号：US13274758

申请日：2011-10-17

申请人： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Wilfried E. Haensch

发明人： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Wilfried E. Haensch

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L21/84 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L27/10867 ,  H01L21/845 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1207 ,  H01L29/0673 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/785

摘要： A memory cell, an array of memory cells, and a method for fabricating a memory cell with multigate transistors such as fully depleted finFET or nano-wire transistors in embedded DRAM. The memory cell includes a trench capacitor, a non-planar transistor, and a self-aligned silicide interconnect electrically coupling the trench capacitor to the non-planar transistor.

摘要翻译： 存储器单元，存储器单元阵列，以及用于制造具有诸如完全耗尽的finFET或嵌入式DRAM中的纳米线晶体管等多重晶体管的存储单元的方法。 存储单元包括沟槽电容器，非平面晶体管和将沟槽电容器电耦合到非平面晶体管的自对准硅化物互连。

公开(公告)号：US09214529B2

公开(公告)日：2015-12-15

申请号：US13047132

申请日：2011-03-14

申请人： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-hsun Lin

发明人： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-hsun Lin

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L29/78 ,  B82Y10/00

CPC分类号： H01L29/66545 ,  B82Y10/00 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7855

摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.

摘要翻译： 一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。

公开(公告)号：US08916054B2

公开(公告)日：2014-12-23

申请号：US13281749

申请日：2011-10-26

申请人： Markus Brink ,  Sebastian U. Engelmann ,  Nicholas C. M. Fuller ,  Michael A. Guillorn ,  Hiroyuki Miyazoe ,  Masahiro Nakamura

发明人： Markus Brink ,  Sebastian U. Engelmann ,  Nicholas C. M. Fuller ,  Michael A. Guillorn ,  Hiroyuki Miyazoe ,  Masahiro Nakamura

IPC分类号： B44C1/22 ,  H01L21/033 ,  H01L21/311 ,  G03F7/40 ,  G03F7/09

CPC分类号： G03F7/094 ,  G03F7/091 ,  G03F7/40 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  Y10T428/24479

摘要： A stack of a hard mask layer, a soft mask layer, and a photoresist is formed on a substrate. The photoresist is patterned to include at least one opening. The pattern is transferred into the soft mask layer by an anisotropic etch, which forms a carbon-rich polymer that includes more carbon than fluorine. The carbon-rich polymer can be formed by employing a fluorohydrocarbon-containing plasma generated with fluorohydrocarbon molecules including more hydrogen than fluorine. The carbon-rich polymer coats the sidewalls of the soft mask layer, and prevents widening of the pattern transferred into the soft mask. The photoresist is subsequently removed, and the pattern in the soft mask layer is transferred into the hard mask layer. Sidewalls of the hard mask layer are coated with the carbon-rich polymer to prevent widening of the pattern transferred into the hard mask.

摘要翻译： 在基板上形成硬掩模层，软掩模层和光致抗蚀剂的堆叠。 图案化光致抗蚀剂以包括至少一个开口。 该图案通过各向异性蚀刻转移到软掩模层中，其形成包含比氟更多的碳的富碳聚合物。 富含碳的聚合物可以通过使用包含比氟更多的氢的氟代烃分子产生的含氟代烃等离子体形成。 富含碳的聚合物涂覆软掩模层的侧壁，并且防止转移到软掩模中的图案的加宽。 随后去除光致抗蚀剂，并将软掩模层中的图案转移到硬掩模层中。 用富含碳的聚合物涂覆硬掩模层的侧壁以防止转移到硬掩模中的图案变宽。

公开(公告)号：US08586455B1

公开(公告)日：2013-11-19

申请号：US13471487

申请日：2012-05-15

申请人： Josephine Chang ,  Michael A. Guillorn ,  Balasubramanian Pranatharthiharan ,  Jeffrey William Sleight

发明人： Josephine Chang ,  Michael A. Guillorn ,  Balasubramanian Pranatharthiharan ,  Jeffrey William Sleight

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/76202 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1104 ,  H01L27/1108

摘要： Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins.

摘要翻译： 本发明的实施例提供一种防止相邻半导体器件的电短路的方法。 该方法包括在衬底上形成多个场效应晶体管的多个散热片; 在所述多个翅片的第一和第二翅片之间形成至少一个阻挡结构; 以及从所述多个翅片生长外延膜，所述外延膜从至少所述第一和第二鳍片的侧壁水平延伸并到达位于所述第一和第二鳍片之间的所述阻挡结构。

公开(公告)号：US08492748B2

公开(公告)日：2013-07-23

申请号：US13169542

申请日：2011-06-27

申请人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

发明人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

IPC分类号： H01L29/06 ,  H01L31/00 ,  H01L29/15 ,  H01L51/40

CPC分类号： H01L29/66045 ,  H01L51/055

摘要： A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.

摘要翻译： 一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。 一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。 通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。 一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。 然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。 独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。

公开(公告)号：US08492208B1

公开(公告)日：2013-07-23

申请号：US13344352

申请日：2012-01-05

申请人： Guy Cohen ,  Michael A. Guillorn ,  Conal Eugene Murray

发明人： Guy Cohen ,  Michael A. Guillorn ,  Conal Eugene Murray

IPC分类号： H01L21/00 ,  H01L29/76

CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439

摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

摘要翻译： 提供一种制造FET器件的方法，其包括以下步骤。 纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。 沉积围绕纳米线的HSQ层。 围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。 形成一个或多个保持在纳米线中诱发的应变的栅极。 还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域， 其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。