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    Semiconductor package and method of manufacturing the same
    1.
    发明申请
    Semiconductor package and method of manufacturing the same 有权
    半导体封装及其制造方法

    公开(公告)号：US20050275074A1

    公开(公告)日：2005-12-15

    申请号：US10868495

    申请日：2004-06-14

    申请人： Gwo-Liang Weng ,  Yung-Li Lu ,  Chi-Chih Chu ,  Shih-Chang Lee

    发明人： Gwo-Liang Weng ,  Yung-Li Lu ,  Chi-Chih Chu ,  Shih-Chang Lee

    IPC分类号： H01L23/02 ,  H05K3/30

    CPC分类号： H05K3/305 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K2201/10734 ,  H05K2203/0545 ,  Y02P70/613 ,  H01L2924/00014

    摘要： A semiconductor package comprising a substrate and a semiconductor device disposed on the substrate by flip-chip bonding. The present invention is characterized by a connection structure disposed between the semiconductor device and the substrate that extends along the periphery of the bottom surface of the semiconductor device. As a result, it can preferably provide additional mounting support between the two. The connection structure can be formed from cured adhesive. The present invention also provides a method of manufacturing the semiconductor package.

    摘要翻译： 一种半导体封装，包括通过倒装芯片接合设置在衬底上的衬底和半导体器件。 本发明的特征在于设置在半导体器件和基板之间的连接结构，该连接结构沿着半导体器件的底表面的周边延伸。 结果，它可以优选地在两者之间提供附加的安装支撑。 连接结构可以由固化的粘合剂形成。 本发明还提供一种半导体封装的制造方法。

    Semiconductor package
    2.
    发明授权
    Semiconductor package 有权
    半导体封装

    公开(公告)号：US07126221B2

    公开(公告)日：2006-10-24

    申请号：US10868495

    申请日：2004-06-14

    申请人： Gwo-Liang Weng ,  Yung-Li Lu ,  Chi-Chih Chu ,  Shih-Chang Lee

    发明人： Gwo-Liang Weng ,  Yung-Li Lu ,  Chi-Chih Chu ,  Shih-Chang Lee

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40

    CPC分类号： H05K3/305 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K2201/10734 ,  H05K2203/0545 ,  Y02P70/613 ,  H01L2924/00014

    摘要： A semiconductor package comprising a substrate and a semiconductor device disposed on the substrate by flip-chip bonding. The present invention is characterized by a connection structure disposed between the semiconductor device and the substrate that extends along the periphery of the bottom surface of the semiconductor device. As a result, it can preferably provide additional mounting support between the two. The connection structure can be formed from cured adhesive. The present invention also provides a method of manufacturing the semiconductor package.

    摘要翻译： 一种半导体封装，包括通过倒装芯片接合设置在衬底上的衬底和半导体器件。 本发明的特征在于设置在半导体器件和基板之间的连接结构，该连接结构沿着半导体器件的底表面的周边延伸。 结果，它可以优选地在两者之间提供附加的安装支撑。 连接结构可以由固化的粘合剂形成。 本发明还提供一种半导体封装的制造方法。

    Chip package
    4.
    发明申请
    Chip package 有权
    芯片封装

    公开(公告)号：US20070222041A1

    公开(公告)日：2007-09-27

    申请号：US11642682

    申请日：2006-12-21

    申请人： Gwo-Liang Weng ,  Yung-Li Lu

    发明人： Gwo-Liang Weng ,  Yung-Li Lu

    IPC分类号： H01L23/495

    CPC分类号： H01L27/14618 ,  H01L21/568 ,  H01L23/3157 ,  H01L24/48 ,  H01L27/14683 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1815 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A chip package including a package substrate, a chip, several bonding wires, a flash-resisting ring and a molding compound. The package substrate includes a carrying surface and several contacts disposed on the carrying surface. The chip is disposed on the carrying surface. A surface of the chip away from the package substrate includes an active region and several bonding pads. The bonding pads are located outside the active region. The bonding wires connect the bonding pads and the contacts. The flash-resisting ring disposed on the chip is located between the bonding pads and the active region. The flash-resisting ring surrounding the active region includes at least one buffer groove. The buffer groove surrounds the active region. The molding compound disposed on the package substrate and the chip encapsulates at least the bonding pads, the contacts and the bonding wires. The molding compound exposes the active region.

    摘要翻译： 一种芯片封装，其包括封装基板，芯片，若干接合线，耐闪光环和模塑料。 封装基板包括承载表面和设置在承载表面上的若干触点。 芯片设置在承载表面上。 远离封装衬底的芯片的表面包括有源区和多个焊盘。 接合焊盘位于有源区域之外。 接合线连接接合焊盘和触点。 布置在芯片上的防闪烁环位于接合焊盘和有源区域之间。 围绕有源区的闪光环包括至少一个缓冲槽。 缓冲槽围绕有源区域。 配置在封装基板和芯片上的模塑料至少封装了焊盘，触点和接合线。 模塑料暴露活性区域。

    Sensor chip packaging structure
    6.
    发明申请
    Sensor chip packaging structure 有权
    传感器芯片封装结构

    公开(公告)号：US20060091515A1

    公开(公告)日：2006-05-04

    申请号：US11163869

    申请日：2005-11-02

    申请人： Gwo-Liang Weng ,  Yung-Li Lu ,  Ying-Tsai Yeh

    发明人： Gwo-Liang Weng ,  Yung-Li Lu ,  Ying-Tsai Yeh

    IPC分类号： H01L23/02

    CPC分类号： H01L27/14618 ,  G06K9/00013 ,  H01L24/73 ,  H01L27/14636 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A sensor chip for defining an exposed molding region is disclosed. The sensor chip includes a semiconductor chip and a metal dam bar protruding from the active surface of the semiconductor chip. The active surface of the semiconductor chip includes a sensing region and at least one bonding pad is disposed on the active surface. The metal dam bar separates the sensing region and the bonding pad to prevent contamination of the sensing region by the mold flash. Preferably, a step is formed on the periphery of the active surface of the semiconductor chip, such that the semiconductor chip includes a T-shaped profile. Additionally, the metal dam bar is extended to the step to form an enclosed ring thereby effectively defining an exposed molding region that contains the sensing region.

    摘要翻译： 公开了一种用于限定暴露的成型区域的传感器芯片。 传感器芯片包括从半导体芯片的有源表面突出的半导体芯片和金属阻挡条。 半导体芯片的有源表面包括感测区域，并且至少一个焊盘设置在有源表面上。 金属阻挡条分隔感测区域和接合焊盘，以防止模具闪光灯对感测区域的污染。 优选地，在半导体芯片的有源表面的周围形成台阶，使得半导体芯片包括T形轮廓。 此外，金属阻挡杆延伸到台阶以形成封闭的环，从而有效地限定包含感测区域的暴露的模制区域。

    Sensor chip packaging structure
    7.
    发明授权
    Sensor chip packaging structure 有权
    传感器芯片封装结构

    公开(公告)号：US07187067B2

    公开(公告)日：2007-03-06

    申请号：US11163869

    申请日：2005-11-02

    申请人： Gwo-Liang Weng ,  Yung-Li Lu ,  Ying-Tsai Yeh

    发明人： Gwo-Liang Weng ,  Yung-Li Lu ,  Ying-Tsai Yeh

    IPC分类号： H01L23/02

    CPC分类号： H01L27/14618 ,  G06K9/00013 ,  H01L24/73 ,  H01L27/14636 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00012

    摘要： A sensor chip for defining an exposed molding region is disclosed. The sensor chip includes a semiconductor chip and a metal dam bar protruding from the active surface of the semiconductor chip. The active surface of the semiconductor chip includes a sensing region and at least one bonding pad is disposed on the active surface. The metal dam bar separates the sensing region and the bonding pad to prevent contamination of the sensing region by the mold flash. Preferably, a step is formed on the periphery of the active surface of the semiconductor chip, such that the semiconductor chip includes a T-shaped profile. Additionally, the metal dam bar is extended to the step to form an enclosed ring thereby effectively defining an exposed molding region that contains the sensing region.

    摘要翻译： 公开了一种用于限定暴露的成型区域的传感器芯片。 传感器芯片包括从半导体芯片的有源表面突出的半导体芯片和金属阻挡条。 半导体芯片的有源表面包括感测区域，并且至少一个焊盘设置在有源表面上。 金属阻挡条分隔感测区域和接合焊盘，以防止模具闪光灯对感测区域的污染。 优选地，在半导体芯片的有源表面的周围形成台阶，使得半导体芯片包括T形轮廓。 此外，金属阻挡杆延伸到台阶以形成封闭的环，从而有效地限定包含感测区域的暴露的模制区域。

    Semiconductor package structure
    8.
    发明授权
    Semiconductor package structure 有权
    半导体封装结构

    公开(公告)号：US07122893B2

    公开(公告)日：2006-10-17

    申请号：US10920077

    申请日：2004-08-17

    申请人： Gwo-Liang Weng ,  Ching-Hui Chang ,  Yung-Li Lu ,  Yu-Wen Chen

    发明人： Gwo-Liang Weng ,  Ching-Hui Chang ,  Yung-Li Lu ,  Yu-Wen Chen

    IPC分类号： H01L23/04

    CPC分类号： H01L24/32 ,  H01L21/563 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/10155

    摘要： A semiconductor package structure includes a semiconductor component, a substrate, solder bumps, underfill, a buffer means, and solder balls. The substrate is under the semiconductor component. A joint area is formed between the first surface of the semiconductor and the upper surface of the substrate. Several solder bumps are disposed in the joint area, for electrically connecting the semiconductor component and the substrate. The underfill is filled in the joint area, for coating the solder bumps and tightly jointing the semiconductor component and the substrate. The buffer means is situated in the jointing area, for buffering the underfill to be confined in the joint area. Several solder balls are disposed on the lower surface of the substrate.

    摘要翻译： 半导体封装结构包括半导体部件，衬底，焊料凸块，底部填充物，缓冲装置和焊球。 衬底在半导体部件下。 在半导体的第一表面和基板的上表面之间形成接合区域。 在接合区域设置有几个焊料凸块，用于电连接半导体部件和基板。 底部填充物填充在接合区域中，用于涂覆焊料凸块并紧密接合半导体部件和基板。 缓冲装置位于接合区域中，用于缓冲封闭在接合区域中的底部填充物。 几个焊球设置在基板的下表面上。

    Chip package with a ring having a buffer groove that surrounds the active region of a chip
    9.
    发明授权
    Chip package with a ring having a buffer groove that surrounds the active region of a chip 有权
    具有环的芯片封装具有环绕芯片的有源区的缓冲槽

    公开(公告)号：US07547962B2

    公开(公告)日：2009-06-16

    申请号：US11642682

    申请日：2006-12-21

    申请人： Gwo-Liang Weng ,  Yung-Li Lu

    发明人： Gwo-Liang Weng ,  Yung-Li Lu

    IPC分类号： H01L23/02 ,  H01L21/00

    CPC分类号： H01L27/14618 ,  H01L21/568 ,  H01L23/3157 ,  H01L24/48 ,  H01L27/14683 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/1815 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A chip package including a package substrate, a chip, several bonding wires, a flash-resisting ring and a molding compound. The package substrate includes a carrying surface and several contacts disposed on the carrying surface. The chip is disposed on the carrying surface. A surface of the chip away from the package substrate includes an active region and several bonding pads. The bonding pads are located outside the active region. The bonding wires connect the bonding pads and the contacts. The flash-resisting ring disposed on the chip is located between the bonding pads and the active region. The flash-resisting ring surrounding the active region includes at least one buffer groove. The buffer groove surrounds the active region. The molding compound disposed on the package substrate and the chip encapsulates at least the bonding pads, the contacts and the bonding wires. The molding compound exposes the active region.

    摘要翻译： 一种芯片封装，其包括封装基板，芯片，若干接合线，耐闪光环和模塑料。 封装基板包括承载表面和设置在承载表面上的若干触点。 芯片设置在承载表面上。 远离封装衬底的芯片的表面包括有源区和多个焊盘。 接合焊盘位于有源区域之外。 接合线连接接合焊盘和触点。 布置在芯片上的防闪烁环位于接合焊盘和有源区域之间。 围绕有源区的闪光环包括至少一个缓冲槽。 缓冲槽围绕有源区域。 配置在封装基板和芯片上的模塑料至少封装了焊盘，触点和接合线。 模塑料暴露活性区域。

    STACKABLE SEMICONDUCTOR PACKAGE
    10.
    发明申请
    STACKABLE SEMICONDUCTOR PACKAGE 有权
    可堆叠半导体封装

    公开(公告)号：US20070246815A1

    公开(公告)日：2007-10-25

    申请号：US11616277

    申请日：2006-12-26

    申请人： Yung-Li Lu ,  Gwo-Liang Weng

    发明人： Yung-Li Lu ,  Gwo-Liang Weng

    IPC分类号： H01L23/02

    CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

    摘要： The present invention relates to a stackable semiconductor package, comprising a first substrate, a chip, a second substrate, a plurality of second wires, a plurality of supporting elements and a molding compound. The chip is disposed on and electrically connected to the first substrate. The second substrate is disposed above the chip, and the area of the second substrate is larger than that of the chip. The second substrate is electrically connected to the first substrate by the second wires. The supporting elements are disposed between the first substrate and the second substrate, and are used for supporting the second substrate. The molding compound encapsulates the first surface of the first substrate, the chip, the second wires, the supporting elements and part of the second substrate, and exposes a surface of the second substrate. The overhang portion of the second substrate will not shake or sway during wire bonding process.

    摘要翻译： 本发明涉及一种可堆叠半导体封装，其包括第一基板，芯片，第二基板，多个第二布线，多个支撑元件和模塑料。 芯片设置在第一基板上并与第一基板电连接。 第二基板设置在芯片上方，第二基板的面积大于芯片的面积。 第二基板通过第二导线与第一基板电连接。 支撑元件设置在第一基板和第二基板之间，并用于支撑第二基板。 模塑料封装第一衬底的第一表面，芯片，第二电线，支撑元件和第二衬底的一部分，并暴露第二衬底的表面。 在引线接合过程中，第二基板的突出部分将不会摇动或摆动。