公开(公告)号：US20090135659A1

公开(公告)日：2009-05-28

申请号：US11945785

申请日：2007-11-27

申请人： Gwyn Robert Jones ,  Mark W. Randolph ,  John Darilek ,  Sean O'Mullan ,  Jacob Marcantel ,  Rick Anundson ,  Adam Shackleton ,  Xiaojian Chu ,  Abhijit Raghunathan ,  Asif Arfi ,  Gulzar Ahmed Kathawala ,  Zhizheng Liu ,  Sung-Chul Lee

发明人： Gwyn Robert Jones ,  Mark W. Randolph ,  John Darilek ,  Sean O'Mullan ,  Jacob Marcantel ,  Rick Anundson ,  Adam Shackleton ,  Xiaojian Chu ,  Abhijit Raghunathan ,  Asif Arfi ,  Gulzar Ahmed Kathawala ,  Zhizheng Liu ,  Sung-Chul Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/14 ,  G11C16/3404 ,  G11C16/3409

摘要： Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift

摘要翻译： 本文提供了在闪存单元中抑制室温电子漂移。 例如，可以在擦除脉冲之后立即对闪存单元施加软编程脉冲。 软编程脉冲可以帮助缓解存储单元中非组合电子和空穴引起的偶极效应。 具体地，通过利用相对低的栅极电压，软编程脉冲可以将电子注入到与擦除脉冲相关联的未组合孔的分布附近的闪存单元中，以便于这种颗粒的快速组合。 以这种方式快速组合可减少由存储单元内的相反电荷的非组合分布引起的偶极效应，从而降低室温程序状态漂移

公开(公告)号：US07944746B2

公开(公告)日：2011-05-17

申请号：US11945785

申请日：2007-11-27

申请人： Gwyn Robert Jones ,  Mark W Randolph ,  John Darilek ,  Sean O'Mullan ,  Jacob Marcantel ,  Rick Anundson ,  Adam Shackleton ,  Xiaojian Chu ,  Abhijit Raghunathan ,  Asif Arfi ,  Gulzar Ahmed Kathawala ,  Zhizheng Liu ,  Sung-Chul Lee

发明人： Gwyn Robert Jones ,  Mark W Randolph ,  John Darilek ,  Sean O'Mullan ,  Jacob Marcantel ,  Rick Anundson ,  Adam Shackleton ,  Xiaojian Chu ,  Abhijit Raghunathan ,  Asif Arfi ,  Gulzar Ahmed Kathawala ,  Zhizheng Liu ,  Sung-Chul Lee

IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/14

CPC分类号： G11C16/14 ,  G11C16/3404 ,  G11C16/3409

摘要： Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.

摘要翻译： 本文提供了在闪存单元中抑制室温电子漂移。 例如，可以在擦除脉冲之后立即对闪存单元施加软编程脉冲。 软编程脉冲可以帮助缓解存储单元中非组合电子和空穴引起的偶极效应。 具体地，通过利用相对低的栅极电压，软编程脉冲可以将电子注入到与擦除脉冲相关联的未组合孔的分布附近的闪存单元中，以便于这种颗粒的快速组合。 以这种方式快速组合可减少由存储单元内的相反电荷的非组合分布引起的偶极效应，从而降低室温程序状态漂移。

公开(公告)号：US07995386B2

公开(公告)日：2011-08-09

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US20090154246A1

公开(公告)日：2009-06-18

申请号：US11956032

申请日：2007-12-13

申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/12

摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

公开(公告)号：US20100128521A1

公开(公告)日：2010-05-27

申请号：US12275663

申请日：2008-11-21

申请人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

发明人： Yuji Mizuguchi ,  Mark W. Randolph ,  Darlene Gay Hamilton ,  Yi He ,  Zhizheng Liu ,  Yanxia (Emma) Lin ,  Xianmin Yi ,  Gulzar Kathawala ,  Amol Ramesh Joshi ,  Kuo-Tung Chang ,  Edward Franklin Runnion ,  Sung-Chul Lee ,  Sung-Yong Chung ,  Yanxiang Liu ,  Yu Sun

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3427

摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。

公开(公告)号：US07746705B2

公开(公告)日：2010-06-29

申请号：US11953689

申请日：2007-12-10

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US07952938B2

公开(公告)日：2011-05-31

申请号：US12773232

申请日：2010-05-04

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US20100208527A1

公开(公告)日：2010-08-19

申请号：US12773232

申请日：2010-05-04

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。

公开(公告)号：US07746698B2

公开(公告)日：2010-06-29

申请号：US11956032

申请日：2007-12-13

申请人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

发明人： Zhizheng Liu ,  An Chen ,  Wei Zheng ,  Kuo-Tung Chang ,  Sung-Yong Chung ,  Gulzar Ahmed Kathawala ,  Ashot Melik-Martirosian

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/12

摘要： Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed.

摘要翻译： 提出了有助于改进非易失性存储器（例如闪速存储器）中的编程存储器单元的系统和方法。 优化的电压分量可以有助于在诸如编程操作的操作期间向与存储器单元相关联的源极，漏极和栅极提供相应的电压。 优化的电压分量可以有助于在单元的编程期间向存储器单元提供预定的源位线电压，以便于减少与位线相关联的泄漏电流，这可以改善存储器单元的编程，并且有助于减少编程电流， 导致功率有效的编程和改进的编程速度。

公开(公告)号：US20090147589A1

公开(公告)日：2009-06-11

申请号：US11953689

申请日：2007-12-10

申请人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

发明人： Gulzar Ahmed Kathawala ,  Wei Zheng ,  Zhizheng Liu ,  Sung-Yong Chung ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Sheung-Hee Park ,  Gabrielle Wing Han Leung

IPC分类号： G11C16/18

CPC分类号： G11C16/3418

摘要： A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

摘要翻译： 提供了一种存储器件，其包括便于擦除基本上均匀的电磁场中的存储器单元的优化部件，以及便于在基本均匀的电磁场中擦除存储器单元的方法。 优化组件有助于同时选择要擦除的存储器单元的子集，使得存储器单元子集中的存储单元具有与存储单元相邻的两个相邻存储器单元，其位于存储器的子集中，或者相邻的一个相邻存储器单元 当存储器单元是端行存储单元时。 优化组件有助于执行Fowler-Nordheim信道擦除来擦除存储器单元的子集，并且与擦除命令相关联的预定电压电位被施加到存储器单元子集的每个单元，以便于减少与电磁场相关联的边缘效应 在擦除期间应用于细胞。