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公开(公告)号：US09196624B2
公开(公告)日：2015-11-24
申请号：US13545469
申请日：2012-07-10
IPC分类号： H01L21/336 , H01L27/115 , H01L21/28
CPC分类号： H01L27/11521 , H01L21/28273
摘要： Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.
摘要翻译： 描述了制作字线保护结构的方法和系统。 如上所述，字线保护结构包括与存储器核心区域相邻形成的多晶硅结构。 多晶硅结构包括位于多晶硅结构的芯侧的第一掺杂区和位于多晶硅结构的脊侧的第二掺杂区。 位于第一和第二掺杂区域之间的未掺杂区域。 导电层形成在多晶硅结构的顶部，并且被布置成使得其在第一掺杂区域和未掺杂区域或第二掺杂区域和未掺杂区域之间的过渡处不接触未掺杂区域。
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2.发明授权公开(公告)号：US08957472B2
公开(公告)日：2015-02-17
申请号：US13357252
申请日：2012-01-24
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译： 提供了存储器件和制造方法。 存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。 栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。 存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。
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3.发明授权公开(公告)号：US08125018B2
公开(公告)日：2012-02-28
申请号：US11033588
申请日：2005-01-12
IPC分类号： H01L29/792
CPC分类号： H01L29/7923 , H01L27/115 , H01L27/11568 , H01L29/66833
摘要： A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
摘要翻译： 提供了存储器件和制造方法。 存储器件包括设置在半导体衬底上的半导体衬底和电荷俘获介质堆叠。 栅电极设置在电荷捕获电介质堆叠之上，其中栅极电极限定半导体衬底的一部分内的沟道。 存储器件包括一对位线，其中位线具有下部分和基本上梯形的上部部分。
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公开(公告)号：US07944746B2
公开(公告)日：2011-05-17
申请号：US11945785
申请日：2007-11-27
申请人： Gwyn Robert Jones , Mark W Randolph , John Darilek , Sean O'Mullan , Jacob Marcantel , Rick Anundson , Adam Shackleton , Xiaojian Chu , Abhijit Raghunathan , Asif Arfi , Gulzar Ahmed Kathawala , Zhizheng Liu , Sung-Chul Lee
发明人： Gwyn Robert Jones , Mark W Randolph , John Darilek , Sean O'Mullan , Jacob Marcantel , Rick Anundson , Adam Shackleton , Xiaojian Chu , Abhijit Raghunathan , Asif Arfi , Gulzar Ahmed Kathawala , Zhizheng Liu , Sung-Chul Lee
CPC分类号： G11C16/14 , G11C16/3404 , G11C16/3409
摘要： Providing for suppression of room temperature electronic drift in a flash memory cell is provided herein. For example, a soft program pulse can be applied to the flash memory cell immediately after an erase pulse. The soft program pulse can help to mitigate dipole effects caused by non-combined electrons and holes in the memory cell. Specifically, by utilizing a relatively low gate voltage, the soft program pulse can inject electrons into the flash memory cell proximate a distribution of uncombined holes associated with the erase pulse in order to facilitate rapid combination of such particles. Rapid combination in this manner reduces dipole effects caused by non-combined distributions of opposing charge within the memory cell, reducing room temperature program state drift.
摘要翻译： 本文提供了在闪存单元中抑制室温电子漂移。 例如，可以在擦除脉冲之后立即对闪存单元施加软编程脉冲。 软编程脉冲可以帮助缓解存储单元中非组合电子和空穴引起的偶极效应。 具体地，通过利用相对低的栅极电压，软编程脉冲可以将电子注入到与擦除脉冲相关联的未组合孔的分布附近的闪存单元中，以便于这种颗粒的快速组合。 以这种方式快速组合可减少由存储单元内的相反电荷的非组合分布引起的偶极效应，从而降低室温程序状态漂移。
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5.发明申请APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB 有权应用负极门电压到相关的字词相关联的阅读或验证，以减少相似词干扰公开(公告)号：US20100128521A1
公开(公告)日：2010-05-27
申请号：US12275663
申请日：2008-11-21
申请人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
发明人： Yuji Mizuguchi , Mark W. Randolph , Darlene Gay Hamilton , Yi He , Zhizheng Liu , Yanxia (Emma) Lin , Xianmin Yi , Gulzar Kathawala , Amol Ramesh Joshi , Kuo-Tung Chang , Edward Franklin Runnion , Sung-Chul Lee , Sung-Yong Chung , Yanxiang Liu , Yu Sun
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3427
摘要： Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.
摘要翻译： 提出了有助于将预定义的负栅极电压施加到与在读取或验证操作期间选择的存储器单元相关联的所选字线相邻的字线的系统，方法和设备，以便于减少相邻字线干扰。 存储器组件可以包括优化的操作部件，其可以至少部分地基于预定义的操作标准，将预定义的负栅极电压施加到与被选择用于读取或验证操作所选择的存储器单元相关联的所选字线相邻的字线上，以便减少 所选择的存储单元中的相邻字线干扰，以便减少电压阈值的移位并保持期望的操作窗口。 优化的操作组件可选地可以包括评估器组件，其可以便于确定施加到相邻字线的负栅极电压是否被调整以便于将相邻字线干扰降低到低于预定阈值量。
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公开(公告)号：US20090161466A1
公开(公告)日：2009-06-25
申请号：US11961772
申请日：2007-12-20
CPC分类号： G11C16/3418 , G11C16/10 , G11C16/3431
摘要： Providing for extended data retention of flash memory devices by program state rewrite is disclosed herein. By way of example, a memory cell or group of memory cells can be evaluated to determine a program state of the cell(s). If the cell(s) is in a program state, as opposed to a natural or non-programmed state, a charge level, voltage level and/or the like can be rewritten to a default level associated with the program state, without erasing the cell(s) first. Accordingly, conventional mechanisms for refreshing cell program state that require rewriting and erasing, typically degrading storage capacity of the memory cell, can be avoided. As a result, data stored in flash memory can be refreshed in a manner that mitigates loss of memory integrity, providing substantial benefits over conventional mechanisms that can degrade memory integrity at a relatively high rate.
摘要翻译： 本文公开了通过程序状态改写提供闪速存储器件的扩展数据保存。 作为示例，可以评估存储器单元或存储器单元组以确定单元的程序状态。 如果单元处于编程状态，与自然或非编程状态相反，则可以将充电电平，电压电平和/或类似物重写为与程序状态相关联的默认电平，而不擦除 电池第一。 因此，可以避免用于刷新需要重写和擦除的通常降低存储器单元的存储容量的小区程序状态的常规机制。 结果，存储在闪速存储器中的数据可以以减轻内存完整性损失的方式刷新，相对于可以以相对较高的速率降低存储器完整性的传统机制提供实质的益处。
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公开(公告)号：US07001807B1
公开(公告)日：2006-02-21
申请号：US10997345
申请日：2004-11-24
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/512 , H01L29/517 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
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8.发明授权Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance 失效制造平面结构电荷捕获具有矩形栅极的存储单元阵列并降低位线电阻的方法公开(公告)号：US06855608B1
公开(公告)日：2005-02-15
申请号：US10463643
申请日：2003-06-17
申请人： Mark Ramsbey , Mark W. Randolph , Jean Yee-Mei Yang , Hiroyuki Kinoshita , Cyrus Tabery , Jeff P. Erhardt , Tazrien Kamal , Jaeyong Park , Emmanuil H. Lingunis
发明人： Mark Ramsbey , Mark W. Randolph , Jean Yee-Mei Yang , Hiroyuki Kinoshita , Cyrus Tabery , Jeff P. Erhardt , Tazrien Kamal , Jaeyong Park , Emmanuil H. Lingunis
IPC分类号： G11C16/04 , H01L21/336 , H01L21/8246 , H01L27/105
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , H01L27/105 , H01L27/11573
摘要： A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.
摘要翻译： 制造具有矩形栅极的平面架构电荷俘获介质存储单元阵列的方法包括在衬底的表面上制造多层电荷俘获电介质。 与衬底相邻的层可以是氧化物。 在电荷捕获电介质上沉积多晶硅层。 在多晶硅层上施加字线掩模以在第一方向上屏蔽线性字线并且在其间露出沟槽区域，并且蚀刻沟槽以暴露沟槽区域中的电荷俘获电介质。 将位线掩模施加在多晶硅层上以在垂直于第一方向的第二方向上屏蔽栅极，并在其间暴露位线区域，并蚀刻位线以暴露位线区域中的氧化物。 植入位线，并在暴露的侧壁上制造绝缘间隔物。 去除氧化物以在位线区域中的绝缘间隔物之间露出衬底，并且在其上制造导体以增强每个位线的导电性。
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9.发明授权Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array 有权用于读取与非易失性存储单元阵列的非活动区域相邻的非易失性存储单元的方法公开(公告)号：US06771545B1
公开(公告)日：2004-08-03
申请号：US10353558
申请日：2003-01-29
申请人： Edward Hsia , Eric Ajimine , Darlene G. Hamilton , Pauling Chen , Ming-Huei Shieh , Mark W. Randolph , Edward Runnion , Yi He
发明人： Edward Hsia , Eric Ajimine , Darlene G. Hamilton , Pauling Chen , Ming-Huei Shieh , Mark W. Randolph , Edward Runnion , Yi He
IPC分类号： G11C1604
CPC分类号： G11C29/82 , G11C16/0491 , G11C16/3404
摘要： An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.
摘要翻译： 非易失性存储器单元的阵列包括有效的单元格列，其中数据模式可以存储在与不存储数据的损坏或非活动列相邻的位置。 存储数据模式并在其中再现数据模式的方法包括将电荷存储在活动列内的所选择的多个存储单元内。 所选择的多个存储单元表示数据模式的一部分。 识别非活动存储器单元编程模式。 非活动存储器单元编程模式识别要在其中存储电荷的所述非活动列中的所有或选定的多个存储单元，以便在存储单元的第一非活动列中周期性地存储电荷以防止过度擦除， 在批量擦除期间以及从非活性电池泄漏到相邻的活性电池。 在第一非活动列中的所选择的多个存储器单元上存储电荷。 读取在第一活动列内的每个存储单元的数据模式。
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公开(公告)号：US20140015138A1
公开(公告)日：2014-01-16
申请号：US13545469
申请日：2012-07-10
CPC分类号： H01L27/11521 , H01L21/28273
摘要： Methods and systems of fabricating a wordline protection structure are described. As described, the wordline protection structure includes a polysilicon structure formed adjacent to a memory core region. The polysilicon structure includes first doped region positioned on a core side of the polysilicon structure and a second doped region positioned on a spine side of the polysilicon structure. An un-doped region positioned between the first and second doped regions. A conductive layer is formed on top of the polysilicon structure and arranged so that it does not contact the un-doped region at either the transition between the first doped region and the un-doped region or the second doped region and un-doped region.
摘要翻译： 描述了制作字线保护结构的方法和系统。 如上所述，字线保护结构包括与存储器核心区域相邻形成的多晶硅结构。 多晶硅结构包括位于多晶硅结构的芯侧的第一掺杂区和位于多晶硅结构的脊侧的第二掺杂区。 位于第一和第二掺杂区域之间的未掺杂区域。 导电层形成在多晶硅结构的顶部，并且被布置成使得其在第一掺杂区域和未掺杂区域或第二掺杂区域和未掺杂区域之间的过渡处不接触未掺杂区域。
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