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    Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties
    1.
    发明授权
    Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties 有权
    具有存储单元晶体管的存储器件的制造方法，其具有不同介电特性的栅极侧壁间隔物

    公开(公告)号：US07560353B2

    公开(公告)日：2009-07-14

    申请号：US11626495

    申请日：2007-01-24

    申请人： Gyu-chul Kim ,  Sung-bong Kim

    发明人： Gyu-chul Kim ,  Sung-bong Kim

    IPC分类号： H01L21/8239

    CPC分类号： H01L29/4983 ,  H01L21/28273 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S257/90

    摘要： A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and second sidewall spacers are disposed on respective ones of the first and second sidewalls of the gate electrode. The first and second sidewall spacers have different dielectric constants. The first and second sidewall spacers may be substantially symmetrical and/or have substantially the same thickness.

    摘要翻译： 诸如DRAM，SRAM或非易失性存储器件的存储器件包括衬底，设置在衬底上的栅极电极以及与栅电极相邻的第一和第二侧壁相邻的衬底中的源极和漏极区域。 第一和第二侧壁间隔物设置在栅电极的第一和第二侧壁的相应的一个上。 第一和第二侧壁间隔物具有不同的介电常数。 第一和第二侧壁间隔物可以是基本对称的和/或具有基本相同的厚度。

    METHODS OF FABRICATING MEMORY DEVICES WITH MEMORY CELL TRANSISTORS HAVING GATE SIDEWALL SPACERS WITH DIFFERENT DIELECTRIC PROPERTIES
    3.
    发明申请
    METHODS OF FABRICATING MEMORY DEVICES WITH MEMORY CELL TRANSISTORS HAVING GATE SIDEWALL SPACERS WITH DIFFERENT DIELECTRIC PROPERTIES 有权
    具有具有不同介电特性的门极间隔的存储器单元晶体管的存储器件的制造方法

    公开(公告)号：US20070122970A1

    公开(公告)日：2007-05-31

    申请号：US11626495

    申请日：2007-01-24

    申请人： Gyu-chul Kim ,  Sung-bong Kim

    发明人： Gyu-chul Kim ,  Sung-bong Kim

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/4983 ,  H01L21/28273 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835 ,  Y10S257/90

    摘要： A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and second sidewall spacers are disposed on respective ones of the first and second sidewalls of the gate electrode. The first and second sidewall spacers have different dielectric constants. The first and second sidewall spacers may be substantially symmetrical and/or have substantially the same thickness.

    摘要翻译： 诸如DRAM，SRAM或非易失性存储器件的存储器件包括衬底，设置在衬底上的栅极电极以及与栅电极相邻的第一和第二侧壁相邻的衬底中的源极和漏极区域。 第一和第二侧壁间隔物设置在栅电极的第一和第二侧壁的相应的一个上。 第一和第二侧壁间隔物具有不同的介电常数。 第一和第二侧壁间隔物可以是基本对称的和/或具有基本相同的厚度。

    Wiring structure of semiconductor device and method for manufacturing the same
    5.
    发明授权
    Wiring structure of semiconductor device and method for manufacturing the same 有权
    半导体装置的配线结构及其制造方法

    公开(公告)号：US06355515B1

    公开(公告)日：2002-03-12

    申请号：US09359243

    申请日：1999-07-22

    申请人： Jae-hwan Moon ,  Gyu-chul Kim

    发明人： Jae-hwan Moon ,  Gyu-chul Kim

    IPC分类号： H01L218244

    CPC分类号： H01L21/823475 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823425 ,  H01L27/11

    摘要： A wiring structure of a semiconductor device and a method for manufacturing the same are provided. The wiring structure according to the present invention includes a body formed of a conductive material in a first insulating film on a semiconductor substrate and a protrusion formed of a conductive material in a second insulating film formed on the first insulating film, connected to the upper surface of the body, formed to have a width less than that of the body, and having a planarized upper surface.

    摘要翻译： 提供半导体器件的布线结构及其制造方法。 根据本发明的布线结构包括由半导体衬底上的第一绝缘膜中的导电材料形成的本体和在形成在第一绝缘膜上的第二绝缘膜中的由导电材料形成的突起，其连接到上表面 的身体，形成为具有小于身体的宽度的宽度，并且具有平坦化的上表面。

    MOS transistor having self-aligned well bias area
    6.
    发明授权
    MOS transistor having self-aligned well bias area 失效
    MOS晶体管具有自对准阱偏置区域

    公开(公告)号：US06399987B2

    公开(公告)日：2002-06-04

    申请号：US09774859

    申请日：2001-01-31

    申请人： Gyu-chul Kim

    发明人： Gyu-chul Kim

    IPC分类号： H01L31119

    CPC分类号： H01L21/76897 ,  H01L21/743 ,  H01L29/6659

    摘要： A MOS transistor having a self-aligned well bias area and a method of fabricating the same provide for efficient application of well bias in a highly integrated semiconductor substrate without causing latch-up. The well bias area is formed at a trench, which is formed by etching a semiconductor substrate in a manner of self-alignment, so that well bias can be efficiently applied to the MOS transistor achieving reduction of the area of a chip without degradation of electrical characteristics.

    摘要翻译： 具有自对准阱偏置区域的MOS晶体管及其制造方法提供了在高度集成的半导体衬底中有效地施加阱偏压而不引起闭锁。 阱偏压区形成在通过以自对准的方式蚀刻半导体衬底而形成的沟槽，从而可以将良好的偏压有效地施加到MOS晶体管，从而实现芯片面积的降低而不会降低电气 特点

    Bipolar junction transistors having insulated gate electrodes
    7.
    发明授权
    Bipolar junction transistors having insulated gate electrodes 失效
    具有绝缘栅电极的双极结晶体管

    公开(公告)号：US5717227A

    公开(公告)日：1998-02-10

    申请号：US666025

    申请日：1996-06-19

    申请人： Gyu-chul Kim

    发明人： Gyu-chul Kim

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L27/082 ,  H01L27/102 ,  H01L31/111

    CPC分类号： H01L29/7395

    摘要： Methods of forming bipolar junction transistors include the step of forming insulated gate electrode means adjacent the base region of the transistor so that the majority carrier conductivity of the base region and the gain (.beta.) of the transistor can be modulated in response to a gate bias. The methods can include the steps of forming an insulated gate electrode containing a conductive gate on a face of a substrate and then forming a base region in the substrate. These steps can then be followed by the steps of patterning the insulated gate electrode to define an opening which exposes a first portion of the base region at the face and then forming an emitter electrode in the opening. The emitter electrode and conductive gate are preferably formed to be in electrical contact so that during operation, the potential of the emitter electrode and conductive gate are maintained at the same level. The emitter electrode is preferably a semiconductor containing first conductivity type dopants which can be diffused into the base region to define an emitter region.

    摘要翻译： 形成双极结晶体管的方法包括形成邻近晶体管的基极区域的绝缘栅极电极装置的步骤，使得可以响应于栅极偏置来调制基极区域的多数载流子导电性和晶体管的增益（β） 。 所述方法可以包括以下步骤：在衬底的表面上形成包含导电栅极的绝缘栅极，然后在衬底中形成基极区域。 然后可以采用以下步骤：图案化绝缘栅电极以限定露出基片区域的第一部分的开口，然后在开口中形成发射电极的步骤。 发射电极和导电栅极优选地形成为电接触，使得在操作期间，发射电极和导电栅极的电位保持在相同的水平。 发射电极优选为含有第一导电型掺杂剂的半导体，其可以扩散到基极区域中以限定发射极区域。

    Wiring structure of semiconductor device
    8.
    发明授权
    Wiring structure of semiconductor device 有权
    半导体器件的接线结构

    公开(公告)号：US06759748B2

    公开(公告)日：2004-07-06

    申请号：US10006303

    申请日：2001-12-06

    申请人： Jae-hwan Moon ,  Gyu-chul Kim

    发明人： Jae-hwan Moon ,  Gyu-chul Kim

    IPC分类号： H01L29739

    CPC分类号： H01L21/823475 ,  H01L21/76804 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823425 ,  H01L27/11

    摘要： A wiring structure of a semiconductor device and a method for manufacturing the same are provided. The wiring structure according to the present invention includes a body formed of a first conductive material in a first insulating film on a semiconductor substrate and a protrusion formed of a second conductive material in a second insulating film formed on the first insulating film, connected to the upper surface of the body, formed to have a width less than that of the body, and having a planarized upper surface.

    摘要翻译： 提供半导体器件的布线结构及其制造方法。 根据本发明的布线结构包括由半导体衬底上的第一绝缘膜中的第一导电材料形成的本体和在形成在第一绝缘膜上的第二绝缘膜中的第二导电材料形成的突起， 身体的上表面形成为具有比身体宽度小的宽度，并且具有平坦化的上表面。