公开(公告)号：US09299530B2

公开(公告)日：2016-03-29

申请号：US14425917

申请日：2013-07-31

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Yasumasa Hamana ,  Takaaki Nagata ,  Kimitsugu Nakamura

IPC: H01J31/50 ,  H01J29/86 ,  H01J5/10 ,  H01J29/88 ,  H01J5/08 ,  H01J40/18

CPC classification number: H01J29/86 ,  C23C16/45525 ,  H01J5/08 ,  H01J5/10 ,  H01J29/88 ,  H01J31/50 ,  H01J40/18

Abstract: In an electron tube, an atomic layer deposition method is used to form an electrical resistance film having a stacked structure of electrically insulating layers and electrically conductive layers or a mixed structure of an electrically insulating material and an electrically conductive material, so as to cover the whole of an inner wall surface and an outer wall surface of a second envelope. By use of the atomic layer deposition method, the firm and fine electrical resistance film with a desired resistance can be formed on an insulation surface, without containing a material such as a binder. When the electrical resistance film is provided with slight electrical conductivity, it can suppress occurrence of withstand voltage failure due to electrification of the insulation surface or the like and realize stability of withstand voltage characteristics.

Abstract translation: 在电子管中，使用原子层沉积法形成具有电绝缘层和导电层的叠层结构或电绝缘材料和导电材料的混合结构的电阻膜，以覆盖 整个内壁表面和第二外壳的外壁表面。 通过使用原子层沉积方法，可以在绝缘表面上形成具有所需电阻的牢固且精细的电阻膜，而不含粘合剂等材料。 当电阻膜具有轻微的导电性时，可以抑制由于绝缘表面等引起的耐电压故障的发生，并且实现耐电压特性的稳定性。

公开(公告)号：US10727035B2

公开(公告)日：2020-07-28

申请号：US16624027

申请日：2018-04-10

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Daichi Masuko ,  Yasumasa Hamana ,  Hajime Nishimura ,  Hiroyuki Watanabe

IPC: H01J43/24

Abstract: The present embodiment relates to an electron multiplier having a structure configured to suppress and stabilize a variation of a resistance value in a wider temperature range. In the electron multiplier, a resistance layer sandwiched between a substrate and a secondary electron emitting layer comprised of an insulating material is configured using a single metal layer in which a plurality of metal particles comprised of a metal material whose resistance value has a positive temperature characteristic are two-dimensionally arranged on a layer formation surface, which is coincident with or substantially parallel to a channel formation surface of the substrate, in the state of being adjacent to each other with a part of the first insulating material interposed therebetween.

公开(公告)号：US10818484B2

公开(公告)日：2020-10-27

申请号：US16489004

申请日：2018-01-23

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Takaaki Nagata ,  Yasumasa Hamana ,  Hajime Nishimura ,  Daichi Masuko

IPC: H01J43/24

Abstract: A microchannel plate is provided with a substrate including a front surface, a rear surface, and a side surface, a plurality of channels penetrating from the front surface to the rear surface of the substrate, a first film provided on at least an inner wall surface of the channel, a second film provided on at least a part of the first film, and electrode layers provided on the front surface and the rear surface of the substrate. The first film is made of MgO, the second film is made of SiO2, and the second film is thinner than the first film.

公开(公告)号：US10340129B2

公开(公告)日：2019-07-02

申请号：US15756217

申请日：2016-08-09

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Takaaki Nagata ,  Yasumasa Hamana ,  Hajime Nishimura ,  Kimitsugu Nakamura

IPC: H01J43/24 ,  H01J9/12

Abstract: A microchannel plate is provided with a substrate including a front surface, a rear surface, and a side surface, a plurality of channels penetrating from the front surface to the rear surface of the substrate, a first film provided on at least an inner wall surface of the channel, a second film provided on the first film, and electrode layers provided on the front surface and the rear surface of the substrate. The first film is made of Al2O3. The second film is made of SiO2. The first film is thicker than the second film.

公开(公告)号：US20150279639A1

公开(公告)日：2015-10-01

申请号：US14429894

申请日：2013-07-11

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Kimitsugu Nakamura ,  Yasumasa Hamana ,  Takaaki Nagata

IPC: H01J43/28 ,  H01J9/12 ,  H01J31/50 ,  H01J43/24

CPC classification number: H01J43/28 ,  H01J9/125 ,  H01J31/507 ,  H01J43/246

Abstract: In a micro-channel plate, an electron emission film and an ion barrier film formed on a substrate are integrally formed by the same film formation step. In this structure, the electron emission film and the ion barrier film are made as continuous and firm films and the ion barrier film can be made thinner. Since the ion barrier film is formed on the back side of an organic film, the organic film is exposed during removal of the organic film. This prevents the organic film from remaining and thus suppresses degradation of performance of the ion barrier film due to the residual organic film, so as to suppress ion feedback from the micro-channel plate and achieve a sufficient improvement in life characteristics of an image intensifier.

Abstract translation: 在微通道板中，通过相同的成膜步骤一体地形成在基板上形成的电子发射膜和离子阻挡膜。 在该结构中，将电子发射膜和离子阻挡膜制成为连续且牢固的膜，并且可以使离子阻挡膜更薄。 由于离子阻挡膜形成在有机膜的背面上，有机膜在去除有机膜期间暴露。 这样可以防止有机膜残留，从而抑制由残留的有机膜引起的离子阻挡膜的性能的劣化，从而抑制来自微通道板的离子反馈，并实现图像增强器的寿命特性的充分改善。

公开(公告)号：US20150228439A1

公开(公告)日：2015-08-13

申请号：US14425917

申请日：2013-07-31

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Yasumasa Hamana ,  Takaaki Nagata ,  Kimitsugu Nakamura

IPC: H01J29/86 ,  H01J40/18

CPC classification number: H01J29/86 ,  C23C16/45525 ,  H01J5/08 ,  H01J5/10 ,  H01J29/88 ,  H01J31/50 ,  H01J40/18

Abstract: In an electron tube, an atomic layer deposition method is used to form an electrical resistance film having a stacked structure of electrically insulating layers and electrically conductive layers or a mixed structure of an electrically insulating material and an electrically conductive material, so as to cover the whole of an inner wall surface and an outer wall surface of a second envelope. By use of the atomic layer deposition method, the firm and fine electrical resistance film with a desired resistance can be formed on an insulation surface, without containing a material such as a binder. When the electrical resistance film is provided with slight electrical conductivity, it can suppress occurrence of withstand voltage failure due to electrification of the insulation surface or the like and realize stability of withstand voltage characteristics.

Abstract translation: 在电子管中，使用原子层沉积法形成具有电绝缘层和导电层的叠层结构或电绝缘材料和导电材料的混合结构的电阻膜，以覆盖 整个内壁表面和第二外壳的外壁表面。 通过使用原子层沉积方法，可以在绝缘表面上形成具有所需电阻的坚固和精细的电阻膜，而不含粘合剂等材料。 当电阻膜具有轻微的导电性时，可以抑制由于绝缘表面等引起的耐电压故障的发生，并且实现耐电压特性的稳定性。

公开(公告)号：US09257266B2

公开(公告)日：2016-02-09

申请号：US14429894

申请日：2013-07-11

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Kimitsugu Nakamura ,  Yasumasa Hamana ,  Takaaki Nagata

IPC: H01J43/24 ,  H01J31/50 ,  H01J43/28 ,  H01J9/12

CPC classification number: H01J43/28 ,  H01J9/125 ,  H01J31/507 ,  H01J43/246

Abstract: In a micro-channel plate, an electron emission film and an ion barrier film formed on a substrate are integrally formed by the same film formation step. In this structure, the electron emission film and the ion barrier film are made as continuous and firm films and the ion barrier film can be made thinner. Since the ion barrier film is formed on the back side of an organic film, the organic film is exposed during removal of the organic film. This prevents the organic film from remaining and thus suppresses degradation of performance of the ion barrier film due to the residual organic film, so as to suppress ion feedback from the micro-channel plate and achieve a sufficient improvement in life characteristics of an image intensifier.

Abstract translation: 在微通道板中，通过相同的成膜步骤一体地形成在基板上形成的电子发射膜和离子阻挡膜。 在该结构中，将电子发射膜和离子阻挡膜制成为连续且牢固的膜，并且可以使离子阻挡膜更薄。 由于离子阻挡膜形成在有机膜的背面上，有机膜在去除有机膜期间暴露。 这样可以防止有机膜残留，从而抑制由残留的有机膜引起的离子阻挡膜的性能的劣化，从而抑制来自微通道板的离子反馈，并实现图像增强器的寿命特性的充分改善。

公开(公告)号：US20150235825A1

公开(公告)日：2015-08-20

申请号：US14425810

申请日：2013-07-31

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Takaaki Nagata ,  Yasumasa Hamana ,  Kimitsugu Nakamura

IPC: H01J43/18 ,  H01J43/28

CPC classification number: H01J43/18 ,  H01J43/28

Abstract: In an electron tube, an electrical resistance film having a stacked structure of electrically insulating layers and electrically conductive layers is formed on holding surfaces of bases in insulating substrates. This electrical resistance film is made as a firm and fine film with a desired resistance by use of an atomic layer deposition method, which can suppress electrification of the bases comprised of an insulating material. This makes it feasible to stably maintain withstand voltage characteristics.

Abstract translation: 在电子管中，在绝缘基板的基板的保持面上形成具有电绝缘层和导电层的堆叠结构的电阻膜。 该电阻膜通过使用可以抑制由绝缘材料构成的基体的带电的原子层沉积方法制成具有所需电阻的牢固且细小的膜。 这使得稳定地保持耐压特性成为可能。

公开(公告)号：US11658003B2

公开(公告)日：2023-05-23

申请号：US17430019

申请日：2019-11-22

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Yasumasa Hamana ,  Hiroyuki Watanabe ,  Kenshi Shimano ,  Hiroji Nishizawa

IPC: H01J37/22 ,  H01J9/22

CPC classification number: H01J37/224 ,  H01J9/22

Abstract: A method of manufacturing a phosphor panel includes: forming a phosphor layer having a plurality of phosphor particles on an exit window; forming an organic film on the phosphor layer; forming a metal reflection film on the organic film; forming an oxide film on the metal reflection film; removing the organic film by firing; and forming an oxide film integrally covering a surface of the metal reflection film and surfaces of the phosphor particles by atomic layer deposition.

公开(公告)号：US11170983B2

公开(公告)日：2021-11-09

申请号：US16623517

申请日：2018-04-10

Applicant: HAMAMATSU PHOTONICS K.K.

Inventor： Daichi Masuko ,  Hajime Nishimura ,  Yasumasa Hamana ,  Hiroyuki Watanabe

IPC: H01J43/24

Abstract: The present embodiment relates to an electron multiplier having a structure configured to suppress and stabilize a variation of a resistance value in a wider temperature range. The electron multiplier includes a resistance layer sandwiched between a substrate and a secondary electron emitting layer and configured using a Pt layer two-dimensionally formed on a layer formation surface which is coincident with or substantially parallel to a channel formation surface of the substrate. The resistance layer has a temperature characteristic within a range in which a resistance value at −60° C. is 10 times or less, and a resistance value at +60° C. is 0.25 times or more, relative to a resistance value at a temperature of 20° C.