公开(公告)号：US20240162297A1

公开(公告)日：2024-05-16

申请号：US18494035

申请日：2023-10-25

Applicant: Hitachi, Ltd.

Inventor： Takeru SUTO ,  Keisuke KOBAYASHI ,  Tomoka SUEMATSU ,  Haruka SHIMIZU

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/80

CPC classification number: H01L29/1608 ,  H01L29/0696 ,  H01L29/7832 ,  H01L29/806

Abstract: A silicon carbide semiconductor device includes: a trench formed on an upper surface of a silicon carbide semiconductor substrate; a gate electrode in the trench; an n-type drift layer, a p-type guard region, an n-type semiconductor region to which a source potential is applied, a p-type body layer and an n-type current diffusion region that have a lower impurity concentration than that of the guard region, the n-type drift layer, the p-type guard region, the n-type semiconductor region, the p-type body layer, and the n-type current diffusion region being formed in the silicon carbide semiconductor substrate; and an n-type JFET region that is formed in the silicon carbide semiconductor substrate so as to be separated from the trench and that connects the current diffusion region and the drift layer. The semiconductor region is separated from the drift layer, the current diffusion region, and the JFET region.

公开(公告)号：US20180090574A1

公开(公告)日：2018-03-29

申请号：US15560428

申请日：2015-05-18

Applicant: HITACHI, LTD.

Inventor： Mieko MATSUMURA ,  Junichi SAKANO ,  Naoki TEGA ,  Yuki MORI ,  Haruka SHIMIZU ,  Keisuke KOBAYASHI

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L29/0615 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7802

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

公开(公告)号：US20230142877A1

公开(公告)日：2023-05-11

申请号：US17920484

申请日：2021-02-08

Applicant: HITACHI, LTD.

Inventor： Haruka SHIMIZU ,  Hiromi SHIMAZU

IPC: H01L21/66 ,  H01L25/07 ,  H01L23/367 ,  H01L29/16 ,  H01L29/06 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L22/20 ,  H01L25/072 ,  H01L23/3672 ,  H01L29/1608 ,  H01L29/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68386

Abstract: An accelerated test for applying a high voltage is performed without reducing a manufacturing yield of a semiconductor device using a wide gap semiconductor material. The technical idea in the embodiment is, for example, an idea of performing the accelerated test in the state of a semiconductor wafer to distinguish a latent defect as illustrated in FIG. 4. That is, the technical idea in the embodiment is to perform the accelerated test on a semiconductor chip containing a wide bandgap semiconductor material as a main component not in the state of a semiconductor chip but in the state of the semiconductor wafer.