公开(公告)号：US20240162297A1

公开(公告)日：2024-05-16

申请号：US18494035

申请日：2023-10-25

Applicant: Hitachi, Ltd.

Inventor： Takeru SUTO ,  Keisuke KOBAYASHI ,  Tomoka SUEMATSU ,  Haruka SHIMIZU

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/80

CPC classification number: H01L29/1608 ,  H01L29/0696 ,  H01L29/7832 ,  H01L29/806

Abstract: A silicon carbide semiconductor device includes: a trench formed on an upper surface of a silicon carbide semiconductor substrate; a gate electrode in the trench; an n-type drift layer, a p-type guard region, an n-type semiconductor region to which a source potential is applied, a p-type body layer and an n-type current diffusion region that have a lower impurity concentration than that of the guard region, the n-type drift layer, the p-type guard region, the n-type semiconductor region, the p-type body layer, and the n-type current diffusion region being formed in the silicon carbide semiconductor substrate; and an n-type JFET region that is formed in the silicon carbide semiconductor substrate so as to be separated from the trench and that connects the current diffusion region and the drift layer. The semiconductor region is separated from the drift layer, the current diffusion region, and the JFET region.

公开(公告)号：US20160141371A1

公开(公告)日：2016-05-19

申请号：US14897247

申请日：2013-06-06

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Keisuke KOBAYASHI ,  Koji FUJISAKI ,  Takashi TAKAHAMA

IPC: H01L29/16 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/04 ,  H01L21/02 ,  H01L29/78 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/0465 ,  H01L21/0485 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7811

Abstract: In order to provide a high-performance and reliable silicon carbide semiconductor device, in a silicon carbide semiconductor device including an n-type SiC epitaxial substrate, a p-type body layer, a p-type body layer potential fixing region and a nitrogen-introduced n-type first source region formed in the p-type body layer, an n-type second source region to which phosphorus which has a solid-solubility limit higher than that of nitrogen and is easily diffused is introduced is formed inside the nitrogen-introduced n-type first source region so as to be separated from both of the p-type body layer and the p-type body layer potential fixing region.

Abstract translation: 为了提供高性能和可靠的碳化硅半导体器件，在包括n型SiC外延衬底，p型体层，p型体层电位固定区和氮化硅电极固定区的碳化硅半导体器件中， 引入形成在p型体层中的n型第一源极区域，在氮 - 氮化物区域内形成n型第二源区，其中具有高于氮的固溶度极限的磷并容易扩散的磷， 引入n型第一源极区域以与p型体层电位固定区域和p型体层电位固定区域分离。

公开(公告)号：US20160111499A1

公开(公告)日：2016-04-21

申请号：US14778058

申请日：2013-03-29

Applicant: HITACHI, LTD.

Inventor： Digh HISAMOTO ,  Keisuke KOBAYASHI ,  Naoki TEGA ,  Toshiyuki OHNO ,  Hirotaka HAMAMURA ,  Mieko MATSUMURA

IPC: H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02

CPC classification number: H01L29/1608 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/045 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1033 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/872

Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Abstract translation: 使用SiC衬底的MOSFET具有通过由于热氧化施加机械应力而在表面上形成碳过量层的问题，并且碳过量层降低沟道载流子的迁移率。 在本发明中，（1）除去含有碳 - 碳键的层; （2）通过沉积方法形成栅极绝缘膜; 和（3）晶体表面和绝缘膜之间的界面在短时间内在低温下进行界面处理。 由此，有效地消除了引起特性劣化的碳过量层，同时通过使氧化膜和氧氮化物膜进行界面处理，可以有效地消除悬挂键。

公开(公告)号：US20180090574A1

公开(公告)日：2018-03-29

申请号：US15560428

申请日：2015-05-18

Applicant: HITACHI, LTD.

Inventor： Mieko MATSUMURA ,  Junichi SAKANO ,  Naoki TEGA ,  Yuki MORI ,  Haruka SHIMIZU ,  Keisuke KOBAYASHI

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/36 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/1608 ,  H01L29/0615 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7802

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.