公开(公告)号：US20190190450A1

公开(公告)日：2019-06-20

申请号：US16301471

申请日：2016-08-02

Applicant: HITACHI, LTD.

Inventor： Yasuhiro IKEDA ,  Toru YAZAKI ,  Yutaka UEMATSU

IPC: H03D1/10 ,  H03D1/18 ,  G05F3/26

CPC classification number: H03D1/10 ,  G05F3/262 ,  H03D1/18 ,  H03D2200/0043

Abstract: A change in a detection voltage due to the temperature is suppressed. A detector circuit includes: a first rectification element having an anode to which an input signal is inputted; a second rectification element having a cathode connected with a cathode of the first rectification element and having an anode connected to an output terminal; and a current mirror circuit for supplying a current to the first rectification element, and for supplying a current-mirror current of the current to the second rectification element.

公开(公告)号：US20180196766A1

公开(公告)日：2018-07-12

申请号：US15740543

申请日：2015-09-18

Applicant: Hitachi, Ltd.

Inventor： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Masatsugu OSHIMI

IPC: G06F13/16

CPC classification number: G06F13/1684 ,  G06F13/1605 ,  G06F13/1694

Abstract: In a memory controller, command, address and data are allocated to transmit the command, the address and the data to each of the plurality of memory devices through the same bus signal line and an identification signal to identify the command, the address and the data on the bus signal line is allocated to a memory common signal line in common among the plurality of memory devices to transmit the identification signal. When the memory controller indicates the data through the identification signal so as to make a first memory device transfer the data through the bus signal line, the memory controller makes the data transfer by the first memory device suspended, indicates the command through the identification signal so as to issue the command to a second memory device, and indicates the address through the identification signal so as to issue the address to the second memory device.

公开(公告)号：US20220013937A1

公开(公告)日：2022-01-13

申请号：US17328551

申请日：2021-05-24

Applicant: Hitachi, Ltd.

Inventor： Norio CHUJO ,  Yasuhiro IKEDA

IPC: H01R12/59 ,  H05K1/14 ,  H05K1/02 ,  H01R12/65 ,  H05K3/32

Abstract: A wiring substrate is connected to a backplane, and includes: a first connector that is mounted on one surface of the wiring substrate and is connected to the backplane; an opening portion that is formed in the one surface on a side opposite to a side connected to the backplane of the first connector, and through which a cable having one end connected to the first connector is passed; an integrated circuit that is mounted on the one surface on a side opposite to a side on which the first connector is present relative to the opening portion; and a second connector that is mounted on the other surface on a side opposite to the one surface in the vicinity of the integrated circuit on the side opposite to the side on which the first connector is present relative to the opening portion, is connected to the integrated circuit via a through hole penetrating the wiring substrate, and is connected to the other end of the cable.

公开(公告)号：US20170286345A1

公开(公告)日：2017-10-05

申请号：US15510486

申请日：2014-11-07

Applicant: HITACHI, LTD.

Inventor： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Hideyuki KOSEKI ,  Masato SHIMIZU ,  Nobushige NAKAJIMA

IPC: G06F13/40 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F13/4022 ,  G06F12/0246 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1056 ,  G06F2212/263 ,  G06F2212/7208 ,  G11C5/066 ,  G11C7/1063 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26

Abstract: A semiconductor memory device includes, in addition to a first switching circuit with which a data system signal line between a plurality of semiconductor memory portions and a memory controller is branched, a second switching circuit with which a non-data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and the first and second switching circuits share a switching signal line.

公开(公告)号：US20190073330A1

公开(公告)日：2019-03-07

申请号：US16093664

申请日：2016-09-26

Applicant: HITACHI, LTD.

Inventor： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Shungo OKABE ,  Akihiro INAMURA ,  Takahiko IWASAKI ,  Junji OGAWA

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/02 ,  G06F3/06

Abstract: To increase the number of selectable chips without adding a signal line to a general purpose memory controller. A semiconductor storage device includes a memory controller, a plurality of memory chips, a selection unit which is connected to the memory controller and is connected with the plurality of memory chips to be able to select any one of the plurality of memory chips, and a switch unit which is connected to the memory controller and the selection unit. The memory controller and the selection unit are connected by a signal line for transmitting a first signal outputted from the memory controller and configured to select the memory chips. The memory controller and the switch unit are connected by a signal line for transmitting a second signal outputted from the memory controller and configured to select the memory chips.

公开(公告)号：US20170220492A1

公开(公告)日：2017-08-03

申请号：US15114424

申请日：2014-05-16

Applicant: HITACHI, LTD.

Inventor： Yasuhiro IKEDA ,  Satoshi MURAOKA

IPC: G06F13/16 ,  G11C29/10 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/102 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/42 ,  G11C7/1045 ,  G11C7/1063 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10 ,  G11C29/12005 ,  G11C29/24 ,  G11C29/50008 ,  G11C2029/1208 ,  G11C2029/5002 ,  G11C2029/5004 ,  G11C2029/5006 ,  G11C2207/2254 ,  H04L25/02 ,  H04L25/03

Abstract: A storage system includes a controller part, a data storage part, and a transfer path of a signal that couples these parts. A driver included in the controller part transmits the signal including write data on the basis of a configured parameter, a receiver included in the data storage part receives the signal, and the write data included in the signal is written into a first storage area. The controller part reads the write data from the first storage area, determines whether or not a bit error exists in the write data, changes the parameter when the bit error exists to repeat similar determination and find an appropriate parameter at which the bit error no longer exists.