公开(公告)号：US20230297265A1

公开(公告)日：2023-09-21

申请号：US17945730

申请日：2022-09-15

Applicant: Hitachi, Ltd.

Inventor： Hideyuki KOSEKI ,  Akira DEGUCHI ,  Masahiro ARAI

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0683 ,  G06F3/0635 ,  G06F3/0604

Abstract: An administrative terminal receives designation of generation target data and of a generation destination storage device and identifies data similar to the target data. The terminal calculates a first predicted time expected for transmitting the target data from a storage device holding the target data to the generation destination storage device, and a second predicted time expected to be required for a second transmission process of transmitting the similar data from an object storage service to the generation destination storage device and of transmitting difference data between the target data and the similar data from the storage device holding the target data to the generation destination storage device. If the second predicted time is shorter than the first predicted time, the administrative terminal performs the second transmission process to transmit the similar data and the difference data to the generation destination storage device to generate the generation target data therein.

公开(公告)号：US20190213078A1

公开(公告)日：2019-07-11

申请号：US16327307

申请日：2017-04-03

Applicant: Hitachi, Ltd.

Inventor： Mitsuo DATE ,  Hideyuki KOSEKI ,  Akifumi SUZUKI ,  Masahiro TSURUYA

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1096 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0689 ,  G06F11/10 ,  G06F11/14

Abstract: A storage apparatus includes: a controller; and a plurality of storage drives, wherein the controller issues a read command for specifying a value associated with an error correction mode to a first storage drive of the plurality of storage drives, the first storage drive selects the error correction mode associated with the value specified by the read command from a plurality of error correction modes, the plurality of error correction modes include a first error correction mode and a second error correction mode with a higher correcting capability and a longer maximum delay time than those of the first error correction mode, and the first storage drive executes a read of data from a storage medium in the selected error correction mode.

公开(公告)号：US20210247913A1

公开(公告)日：2021-08-12

申请号：US17011215

申请日：2020-09-03

Applicant: HITACHI, LTD.

Inventor： Hideyuki KOSEKI ,  Tomohiro KAWAGUCHI

IPC: G06F3/06

Abstract: The accuracy of predicting the remaining life of a non-volatile memory in which WA occurs is enhanced. A storage controller predicts the remaining lives of SSDs on the basis of the data storage rates of the respective SSDs. When the storage controller determines that a life expectation result on one SSD does not satisfy a target operation period while a life expectation result on another SSD satisfies the target operation period, the storage controller executes extent migration processing of migrating data in any data stored extent to an extent in which data has not been stored, thereby decreasing the data storage rate of the one SSD to extend the life of the one SSD.

公开(公告)号：US20180011642A1

公开(公告)日：2018-01-11

申请号：US15545743

申请日：2015-04-28

Applicant: HITACHI, LTD.

Inventor： Hideyuki KOSEKI ,  Shigeo HOMMA

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0616 ,  G06F3/0649 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0688 ,  G06F11/1076

Abstract: A storage unit according to one aspect of the present invention comprises a storage controller and a plurality of storage devices. Each storage device has nonvolatile semiconductor memories serving as storage media. The controller of each storage device diagnoses the state of degradation of the nonvolatile semiconductor memories, and if one of the nonvolatile semiconductor memories is expected to be nearing end of life, then the controller copies the data stored in that degraded nonvolatile semiconductor memory to another nonvolatile semiconductor memory, and then performs shutdown processing for the degraded nonvolatile semiconductor memory, as well as storage capacity reduction processing.

公开(公告)号：US20170300381A1

公开(公告)日：2017-10-19

申请号：US15506197

申请日：2014-10-03

Applicant: Hitachi, Ltd.

Inventor： Nagamasa MIZUSHIMA ,  Atsushi KAWAMURA ,  Hideyuki KOSEKI

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/16 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

Abstract: A memory controller includes an error check correction circuit performing a calculation regarding an error correction code of data, and a processor using the error check correction circuit and write the data with the error correction code to a non-volatile memory (NVM) when writing the data to the NVM, while performing error correction of the data using the error correction code when reading the data from the NVM. The processor counts the number of error bits of the data stored in a block that is a unit of batch-erasure of the data, stores the data in the block with a first error correction code having an error correction ability, and stores the data in the block with a second error correction code having an error correction ability higher than the first error correction code when the number of the error bits is larger than a value.

公开(公告)号：US20170286345A1

公开(公告)日：2017-10-05

申请号：US15510486

申请日：2014-11-07

Applicant: HITACHI, LTD.

Inventor： Yasuhiro IKEDA ,  Yutaka UEMATSU ,  Hideyuki KOSEKI ,  Masato SHIMIZU ,  Nobushige NAKAJIMA

IPC: G06F13/40 ,  G11C16/24 ,  G11C16/26

CPC classification number: G06F13/4022 ,  G06F12/0246 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1056 ,  G06F2212/263 ,  G06F2212/7208 ,  G11C5/066 ,  G11C7/1063 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26

Abstract: A semiconductor memory device includes, in addition to a first switching circuit with which a data system signal line between a plurality of semiconductor memory portions and a memory controller is branched, a second switching circuit with which a non-data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and the first and second switching circuits share a switching signal line.

公开(公告)号：US20240419744A1

公开(公告)日：2024-12-19

申请号：US18597166

申请日：2024-03-06

Applicant: Hitachi, Ltd.

Inventor： Hideyuki KOSEKI ,  Akira DEGUCHI ,  Hiroki FUJII

IPC: G06F16/951

Abstract: When data is to be stored in or transferred to a storage system including a controller, the controller causes a selected offload instance to compress or to decompress the data to be stored in or to be transferred to the storage system, the selected offload instance being one or more offload instances that support a specific compression scheme and to which a compression or decompression load is to be offloaded.

公开(公告)号：US20240036989A1

公开(公告)日：2024-02-01

申请号：US18115881

申请日：2023-03-01

Applicant: Hitachi, Ltd.

Inventor： Akira DEGUCHI ,  Masahiro ARAI ,  Hideyuki KOSEKI

IPC: G06F11/14

CPC classification number: G06F11/1469 ,  G06F2201/805

Abstract: A management server stops a sub-server in advance and prepares a sub-storage that operates in response to a request from the sub-server at the time of transition at which a business process of using data stored in a regular storage is performed in the sub-server. The management server recovers data using recovery data stored in an object storage and stores the data in the sub-storage and starts the sub-server.

公开(公告)号：US20220236882A1

公开(公告)日：2022-07-28

申请号：US17477308

申请日：2021-09-16

Applicant: Hitachi, Ltd.

Inventor： Hideyuki KOSEKI ,  Hiroki FUJII ,  Akira DEGUCHI ,  Akira YAMAMOTO

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/10

Abstract: The efficiency of the maintenance of a storage apparatus including a plurality of flash drives can be enhanced.
In a storage apparatus including a plurality of SSDs and a CPU, the CPU specifies, based on lifetimes of the SSDs depending on amounts of data written to the SSDs, the SSD to be replaced on a scheduled maintenance date, gives notice of the SSD specified to be replaced, and copies data in the SSD to be replaced to another SSD by the scheduled maintenance date on which the replacement is to be performed.

公开(公告)号：US20190004942A1

公开(公告)日：2019-01-03

申请号：US16066730

申请日：2016-01-21

Applicant: HITACHI, LTD.

Inventor： Hiroki FUJII ,  Hideyuki KOSEKI ,  Atsushi KAWAMURA

IPC: G06F12/02 ,  G06F12/1009 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/1009 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/403 ,  G06F2212/7201

Abstract: A storage device determines whether or not reading target data subjected to a first conversion process is divided and stored into multiple pages. When the data subjected to the first conversion process is stored in one of a plurality of pages, the data is read from the page, and a second conversion process for returning the data to a state before the data is subjected to the first conversion process is executed to the data. When the reading target data is divided and stored into two or more of the plurality of pages, a portion of the data is read from each of the two or more pages in which the portion of the data is stored, the portion of the data is stored in the buffer memory, the data subjected to the first conversion process is restored, and the second conversion process is executed to the restored data.