公开(公告)号：US20240054385A1

公开(公告)日：2024-02-15

申请号：US17641214

申请日：2021-03-01

Applicant: Hitachi High-Tech Corporation

Inventor： Yuyao Wang ,  Yasuhide Mori ,  Masashi Egi ,  Takeshi Ohmori ,  Satoshi Sakai ,  Kohei Matsuda

IPC: G06N20/00

CPC classification number: G06N20/00

Abstract: For a machine learning model that receives control parameters of a semiconductor processing device and outputs shape parameters that express a processed shape of a semiconductor sample processed by the semiconductor processing device, an experiment point obtaining learning data is recommended. A contribution of each control parameter to the prediction of the machine learning model is evaluated from feature quantity data that is a value of a control parameter of the learning data used for learning of the machine learning model, and the experiment point is recommended based on a stability evaluation and an uncertainty evaluation of the prediction by the machine learning model in a space defined by the control parameters selected based on the contribution as axes.

公开(公告)号：US11557463B2

公开(公告)日：2023-01-17

申请号：US17160801

申请日：2021-01-28

Applicant: Hitachi High-Tech Corporation

Inventor： Hiroyuki Kobayashi ,  Nobuya Miyoshi ,  Kazunori Shinoda ,  Kenji Maeda ,  Yutaka Kouzuma ,  Satoshi Sakai ,  Masaru Izawa

IPC: H01J37/32 ,  H01L21/67

Abstract: In a vacuum processing apparatus including: a vacuum container including a processing chamber therein; a plasma formation chamber; plate members being arranged between the processing chamber and the plasma formation chamber; and a lamp and a window member being arranged around the plate members, in order that a wafer and the plate members are heated by electromagnetic waves from the lamp, a bottom surface and a side surface of the window member is formed of a member transmitting the electromagnetic waves therethrough.

公开(公告)号：US10892158B2

公开(公告)日：2021-01-12

申请号：US16371502

申请日：2019-04-01

Applicant: HITACHI HIGH-TECH CORPORATION

Inventor： Makoto Miura ,  Yohei Ishii ,  Satoshi Sakai ,  Kenji Maeda

IPC: H01L21/02 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/033 ,  H01L27/092

Abstract: A manufacturing process of a semiconductor device including a SiGe channel can form a Si segregation layer for protecting the SiGe channel without damaging the SiGe channel. A manufacturing method of a semiconductor device includes: a first step for performing plasma processing on a semiconductor substrate having a silicon layer and a silicon germanium layer formed on the silicon layer under a first condition to expose the silicon germanium layer; and a second step for performing plasma processing on the semiconductor substrate under a second condition to segregate silicon on the surface of the exposed silicon germanium layer. The silicon germanium layer or layers lying adjacent to the silicon germanium layer can be etched under the first condition, hydrogen plasma processing is performed under the second condition, and the first step and the second step are executed in series in the same processing chamber of a plasma processing apparatus.

公开(公告)号：US12094781B2

公开(公告)日：2024-09-17

申请号：US16971449

申请日：2019-09-13

Applicant: Hitachi High-Tech Corporation

Inventor： Makoto Miura ,  Kiyohiko Sato ,  Yasushi Sonoda ,  Satoshi Sakai

IPC: H01L21/8234 ,  H01J37/32 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/82345 ,  H01J37/32082 ,  H01J37/3244 ,  H01J37/32715 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696 ,  H01J2237/332 ,  H01J2237/334

Abstract: A manufacturing process for a three-dimensional structure device having stacked channels in which channels having a shape of a thin line or a sheet are stacked in a direction vertical to a substrate, a work function control metal is separately formed without expanding a space between FETS having different threshold voltages, and including a first step of performing anisotropic etching to open the mask material until the work function control metal film is exposed; a second step of depositing a protective film; a third step of performing anisotropic etching to remove the protective film while remaining the protective film deposited on sidewalls of the mask material opened in the first step; and a fourth step of performing isotropic etching to selectively remove the mask material between the channels relative to the protective film and the work function control metal film are executed.

公开(公告)号：US20210082766A1

公开(公告)日：2021-03-18

申请号：US16971449

申请日：2019-09-13

Applicant: Hitachi High-Tech Corporation

Inventor： Makoto Miura ,  Kiyohiko Sato ,  Yasushi Sonoda ,  Satoshi Sakai

IPC: H01L21/8234 ,  H01J37/32

Abstract: In a manufacturing process of a three-dimensional structure device such as a GAA type FET or a nanosheet fork type FET having stacked channels in which channels having a shape of a wire or a sheet are stacked in a direction vertical to a substrate, a work function control metal is separately formed without expanding a space between FETs having different threshold voltages. Therefore, a first step S10 of performing anisotropic etching to open the mask material 23 until the work function control metal film 22 is exposed; a second step S11 of depositing a protective film 26; a third step S12 of performing anisotropic etching to remove the protective film while remaining the protective film deposited on sidewalls of the mask material opened in the first step; and a fourth step S13 of performing isotropic etching to selectively remove the mask material between the channels relative to the protective film and the work function control metal film are executed.

公开(公告)号：US11915951B2

公开(公告)日：2024-02-27

申请号：US16913010

申请日：2020-06-26

Applicant: HITACHI HIGH-TECH CORPORATION

Inventor： Hiroyuki Kobayashi ,  Nobuya Miyoshi ,  Kazunori Shinoda ,  Tatehito Usui ,  Naoyuki Kofuji ,  Yutaka Kouzuma ,  Tomoyuki Watanabe ,  Kenetsu Yokogawa ,  Satoshi Sakai ,  Masaru Izawa

IPC: H01L21/67 ,  H01J37/32 ,  C23C16/48 ,  H01L21/66

CPC classification number: H01L21/67248 ,  C23C16/482 ,  H01J37/3299 ,  H01J37/32449 ,  H01J37/32724 ,  H01J37/32917 ,  H01J37/32935 ,  H01J37/32972 ,  H01L21/67069 ,  H01L21/67098 ,  H01L21/67115 ,  H01L21/67207 ,  H01L22/12 ,  H01L22/20 ,  H01J2237/2001 ,  H01J2237/24585 ,  H01J2237/334

Abstract: A plasma processing apparatus includes a stage disposed in a processing chamber for mounting a wafer, a plasma generation chamber disposed above the processing chamber for plasma generation using process gas, a plate member having multiple introduction holes, made of a dielectric material, disposed above the stage and between the processing chamber and the plasma generation chamber, and a lamp disposed around the plate member for heating the wafer. The plasma processing apparatus further includes an external IR light source, an emission fiber arranged in the stage, that outputs IR light from the external IR light source toward a wafer bottom, and a light collection fiber for collecting IR light from the wafer. Data obtained using only IR light from the lamp is subtracted from data obtained also using IR light from the external IR light source during heating of the wafer. Thus, a wafer temperature is determined.