公开(公告)号：US20110244666A1

公开(公告)日：2011-10-06

申请号：US13080288

申请日：2011-04-05

申请人： Ha-Na Kim ,  Gyungjin Min ,  Chulho Shin ,  Sukho Joo ,  Han Geun Yu ,  Yeonghun Han

发明人： Ha-Na Kim ,  Gyungjin Min ,  Chulho Shin ,  Sukho Joo ,  Han Geun Yu ,  Yeonghun Han

IPC分类号： H01L21/302 ,  H01L21/28 ,  H01L21/31

CPC分类号： H01L27/11578 ,  H01L21/033 ,  H01L21/0337 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575

摘要： Methods of manufacturing stair-type structures and methods of manufacturing nonvolatile memory devices using the same. Methods of manufacturing stair-type structures may include forming a plurality of thin layers stacked in plate shapes, forming a mask on an utmost thin layer, patterning the utmost layer using the mask as an etch mask, escalating a width of the mask and etching each of the thin layers at a different width of the mask to form a stair-type structure of the thin layers. Control gates may be formed into the stair-type structures using the methods of manufacturing stair-type structures.

摘要翻译： 制造楼梯型结构的方法和制造使用其的非易失性存储装置的制造方法。 制造阶梯型结构的方法可以包括形成多个以板形形式堆叠的薄层，在最薄层上形成掩模，使用掩模将最大层图案化为蚀刻掩模，增加掩模的宽度并蚀刻每个 在薄膜的不同宽度处的薄层，以形成薄层的阶梯型结构。 可以使用制造楼梯型结构的方法将控制门形成为楼梯型结构。

公开(公告)号：US09564324B2

公开(公告)日：2017-02-07

申请号：US14220440

申请日：2014-03-20

申请人： Eunsung Kim ,  Jaewoo Nam ,  Chulho Shin

发明人： Eunsung Kim ,  Jaewoo Nam ,  Chulho Shin

IPC分类号： H01L21/00 ,  H01L21/027 ,  H01L29/66 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L21/0271 ,  H01L27/10855 ,  H01L27/11582 ,  H01L29/66795

摘要： The inventive concepts provide methods of forming a pattern. In the method, a block copolymer layer may be formed on a neutral layer having an uneven structure and then phase separation is induced. The neutral layer may have an affinity for all of a hydrophilic polymer and a hydrophobic polymer, so that vertical cultivation of phases of the block copolymer may be realized on the uneven structure. Thus, a self-assembled phenomenon may be induced.

摘要翻译： 本发明的概念提供了形成图案的方法。 在该方法中，可以在具有不均匀结构的中性层上形成嵌段共聚物层，然后诱发相分离。 中性层可以对所有亲水性聚合物和疏水性聚合物具有亲和力，从而可以在不均匀结构上实现嵌段共聚物的相的垂直培养。 因此，可能引起自组装现象。

公开(公告)号：US20070038431A1

公开(公告)日：2007-02-15

申请号：US11202363

申请日：2005-08-12

申请人： Simon Yoon ,  Chulho Shin

发明人： Simon Yoon ,  Chulho Shin

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method, system and computer programs for simulating the operation of a data processing apparatus when executing a sequence of instructions is disclosed. The data processing apparatus comprising a plurality of units, each of the units having associated therewith architectural state generated in response to the sequence of instructions. The method comprises the steps of: providing a hardware description model comprising a hardware description component corresponding with at least one of the plurality of units, each hardware description component comprising a hardware characteristic component representing the hardware characteristics of that unit and an architectural state component for storing a representation of any architectural state associated with that unit generated in response to the sequence of instructions; providing a system level model comprising a system level component corresponding with at least one other of the plurality of units, the system level model further comprising at least one shadow architectural state component for storing a representation of any architectural state stored by a corresponding architectural state component of the hardware description model; executing the hardware description model and the system level model to simulate the operation of the data processing apparatus when executing the sequence of instructions; and causing any changes in architectural state stored in the corresponding architectural state component to be also stored by the shadow architectural state component. Accordingly, the status of the architectural state can readily be determined in combination with information from the system level component using tools associated with the system level model. In this way, a correlation can readily be made between the status of the system level component and the architectural state generated by the hardware description model in response to the sequence of instructions. Also, by only causing the shadow architectural state component to store architectural state when architectural state within the architectural state component is updated, the number of updates between the hardware description model and the system level model can be minimized to only those which are required to provide a representation of the current state of the hardware description model. Reducing the number of updates required to be communicated between the two models significantly improves the performance of these models.

公开(公告)号：US08846305B2

公开(公告)日：2014-09-30

申请号：US13537618

申请日：2012-06-29

申请人： Eunsung Kim ,  Kyoungseon Kim ,  Jaewoo Nam ,  Chulho Shin ,  Shiyong Yi

发明人： Eunsung Kim ,  Kyoungseon Kim ,  Jaewoo Nam ,  Chulho Shin ,  Shiyong Yi

IPC分类号： G03F7/26 ,  G03F7/20

CPC分类号： G03F7/20 ,  G03F7/0392 ,  G03F7/2028 ,  G03F7/322 ,  G03F7/325 ,  G03F7/40

摘要： A photolithography method includes coating a photoresist on an active region and an edge region of a wafer, exposing the photoresist on the edge region to first ultraviolet rays, exposing the photoresist on the active region to second ultraviolet rays, depositing a first developing solution on the photoresist on the edge region to remove the photoresist on the edge region, and developing the photoresist on the active region using a second developing solution.

摘要翻译： 光刻方法包括在晶片的有源区域和边缘区域上涂覆光致抗蚀剂，将边缘区域上的光致抗蚀剂暴露于第一紫外线，将活性区域上的光致抗蚀剂暴露于第二紫外线，将第一显影溶液沉积在 在边缘区域上的光致抗蚀剂去除边缘区域上的光致抗蚀剂，并且使用第二显影溶液在活性区域上显影光致抗蚀剂。

公开(公告)号：US20130056823A1

公开(公告)日：2013-03-07

申请号：US13603045

申请日：2012-09-04

申请人： Yoonjae Kim ,  Nam-Gun Kim ,  Chulho Shin ,  Chan Min Lee

发明人： Yoonjae Kim ,  Nam-Gun Kim ,  Chulho Shin ,  Chan Min Lee

IPC分类号： H01L29/78

CPC分类号： H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

摘要： A device isolation layer is formed in a substrate to define spaced-apart linear active regions in the substrate. Buried gate patterns are formed in the substrate and extending along a first direction to cross the active regions. An etch stop layer and a first insulating layer are formed on the substrate. Bit line structures are formed on the first insulating layer and extending along a second direction transverse to the first direction to cross the active regions. A second insulating layer is formed on the bit line structures. Contact plugs are formed penetrating the second insulating layer, the first insulating layer, and the etch stop layer to contact one of the active regions between adjacent ones of the bit line structures.

摘要翻译： 在衬底中形成器件隔离层，以在衬底中限定间隔开的线性有源区。 掩埋栅极图案形成在衬底中并且沿着第一方向延伸以跨过有源区域。 在基板上形成蚀刻停止层和第一绝缘层。 位线结构形成在第一绝缘层上并且沿着横向于第一方向的第二方向延伸以穿过有源区。 在位线结构上形成第二绝缘层。 穿过第二绝缘层，第一绝缘层和蚀刻停止层的接触插塞接触相邻的位线结构中的一个有源区。