公开(公告)号：US07598562B2

公开(公告)日：2009-10-06

申请号：US11769423

申请日：2007-06-27

申请人： Hajime Nagano ,  Takeo Furuhata

发明人： Hajime Nagano ,  Takeo Furuhata

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined on the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes a gate insulating film formed on a surface of the element forming region; a floating gate formed over the gate insulating film; an inter-gate insulating film formed integrally so as to cover the floating gate and the insulating film of the element isolation region and having high dielectric constant in a portion corresponding to the floating gate and low dielectric constant in a portion corresponding to the insulating film of the element isolation region; and a control gate stacked over the floating gate via the inter-gate insulating film.

摘要翻译： 一种半导体器件，包括半导体衬底; 元件隔离区域，其具有填充有限定在所述半导体衬底上的绝缘膜的沟槽; 形成在由所述半导体衬底的元件隔离区隔离的元件形成区域中的存储单元晶体管; 并且所述存储单元晶体管包括形成在所述元件形成区域的表面上的栅极绝缘膜; 形成在栅绝缘膜上的浮栅; 一体地形成栅绝缘膜，以覆盖浮动栅极和元件隔离区域的绝缘膜，并且在对应于浮栅的部分和低介电常数的部分中具有高介电常数，在与绝缘膜相对应的部分 元件隔离区; 以及通过栅极间绝缘膜堆叠在浮置栅极上的控制栅极。

公开(公告)号：US20070296016A1

公开(公告)日：2007-12-27

申请号：US11769423

申请日：2007-06-27

申请人： Hajime Nagano ,  Takeo Furuhata

发明人： Hajime Nagano ,  Takeo Furuhata

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor device including a semiconductor substrate; an element isolation region having a trench filled with an insulating film defined or the semiconductor substrate; a memory cell transistor formed in an element forming region isolated by the element isolating regions of the semiconductor substrate; and the memory cell transistor includes a gate insulating film formed on a surface of the element forming region; a floating gate formed over the gate insulating film; an inter-gate insulating film formed integrally so as to cover the floating gate and the insulating film of the element isolation region and having high dielectric constant in a portion corresponding to the floating gate and low dielectric constant in a portion corresponding to the insulating film of the element isolation region; and a control gate stacked over the floating gate via the inter-gate insulating film.

摘要翻译： 一种半导体器件，包括半导体衬底; 元件隔离区域，其具有填充有限定的绝缘膜的沟槽或半导体衬底; 形成在由所述半导体衬底的元件隔离区隔离的元件形成区域中的存储单元晶体管; 并且所述存储单元晶体管包括形成在所述元件形成区域的表面上的栅极绝缘膜; 形成在栅绝缘膜上的浮栅; 一体地形成栅绝缘膜，以覆盖元件隔离区域的浮栅和绝缘膜，并且在对应于浮栅的部分和低介电常数的部分中具有高介电常数 元件隔离区; 以及通过栅极间绝缘膜堆叠在浮置栅极上的控制栅极。

公开(公告)号：US08017990B2

公开(公告)日：2011-09-13

申请号：US12497955

申请日：2009-07-06

申请人： Hajime Nagano

发明人： Hajime Nagano

IPC分类号： H01L29/788

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory device includes a gate insulating film formed on a semiconductor substrate, a first gate electrode corresponding to a memory cell transistor and a second gate electrode. The first gate electrode includes a floating gate electrode film, a first interelectrode insulating film and a control gate electrode film. The floating gate electrode film has a polycrystalline silicon film and the control gate electrode film having a silicide film. The second gate electrode includes a lower electrode film, a second interelectrode insulating film and an upper electrode film. The second interelectrode insulating film includes an opening. The lower electrode film includes a void below the opening of the second interelectrode insulating film. The upper electrode film includes a silicide film. The lower electrode film includes a polycrystalline silicon film and a silicide film which is located between the opening and the void.

摘要翻译： 非易失性半导体存储器件包括形成在半导体衬底上的栅绝缘膜，对应于存储单元晶体管的第一栅电极和第二栅电极。 第一栅电极包括浮栅电极膜，第一电极间绝缘膜和控制栅电极膜。 浮栅电极膜具有多晶硅膜，并且控制栅电极膜具有硅化物膜。 第二栅电极包括下电极膜，第二电极间绝缘膜和上电极膜。 第二电极间绝缘膜包括开口。 下电极膜在第二电极间绝缘膜的开口下方具有空隙。 上电极膜包括硅化物膜。 下电极膜包括位于开口和空隙之间的多晶硅膜和硅化物膜。

公开(公告)号：US07749455B2

公开(公告)日：2010-07-06

申请号：US10522604

申请日：2003-08-06

申请人： Masahiro Harada ,  Shintaro Honjo ,  Makoto Susaki ,  Kazuo Ishida ,  Hajime Nagano ,  Susumu Okino ,  Kozo Iida ,  Akira Johana

发明人： Masahiro Harada ,  Shintaro Honjo ,  Makoto Susaki ,  Kazuo Ishida ,  Hajime Nagano ,  Susumu Okino ,  Kozo Iida ,  Akira Johana

IPC分类号： G05D7/00 ,  B01D53/04 ,  B01D53/34 ,  B01D53/52 ,  B01D53/86 ,  B01J8/02 ,  B01J35/02 ,  C01B17/00 ,  C01B17/16 ,  C01B31/00 ,  C10G17/00 ,  C10G45/00

CPC分类号： B01J23/866 ,  B01D53/885 ,  C10K1/34

摘要： A COS treatment apparatus for a gasified gas includes an O2 removal catalyst and a COS conversion catalyst located on the downstream side of a gasified gas flow with respect to the O2 removal catalyst. Also, a COS treatment apparatus includes a TiO2 catalyst that carries Cr2O3 or NiO. Further, a COS treatment method includes a first step in which O2 is removed by the reaction with H2S and CO, and a second step in which COS is converted to H2S.

摘要翻译： 用于气化气体的COS处理装置包括相对于除去氧化催化剂的气化气体流的下游侧的除氧催化剂和COS转化催化剂。 此外，COS处理装置包括载持Cr 2 O 3或NiO的TiO 2催化剂。 此外，COS处理方法包括通过与H 2 S和CO的反应除去O 2的第一步骤和将COS转化为H 2 S的第二步骤。

公开(公告)号：US07718483B2

公开(公告)日：2010-05-18

申请号：US11399655

申请日：2006-04-07

申请人： Ichiro Mizushima ,  Hajime Nagano ,  Yoshio Ozawa ,  Hisataka Meguro ,  Takashi Suzuki

发明人： Ichiro Mizushima ,  Hajime Nagano ,  Yoshio Ozawa ,  Hisataka Meguro ,  Takashi Suzuki

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11521

摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.

摘要翻译： 在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。

公开(公告)号：US07265017B2

公开(公告)日：2007-09-04

申请号：US11168914

申请日：2005-06-29

申请人： Hajime Nagano ,  Ichiro Mizushima

发明人： Hajime Nagano ,  Ichiro Mizushima

IPC分类号： H01L21/331

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： There is closed a semiconductor device which comprises a semiconductor substrate including an SOI region where a first insulating film is buried, and a non-SOI region, the semiconductor substrate being provided with a boundary region formed between the SOI region and the non-SOI region and having a second insulating film buried therein, the second insulating film being inclined upward from the SOI region side toward the non-SOI region side, the second insulating film having a thickness smaller than the thickness of the first insulating film and being tapered from the SOI region side to the non-SOI region side, a pair of element isolating insulating regions separately formed in the non-SOI region of semiconductor substrate and defining element regions, a pair of impurity diffusion regions formed in the element regions, and a gate electrode formed via a gate insulating film in the element region of the semiconductor substrate.

摘要翻译： 封闭半导体器件，其包括半导体衬底，该半导体衬底包括掩埋有第一绝缘膜的SOI区域和非SOI区域，该半导体衬底设置有形成在SOI区域与非SOI区域之间的边界区域 并且具有埋置在其中的第二绝缘膜，所述第二绝缘膜从所述SOI区域侧向非SOI区域侧向上倾斜，所述第二绝缘膜的厚度小于所述第一绝缘膜的厚度， SOI区域侧，分离地形成在半导体衬底的非SOI区域中并限定元件区域的一对元件隔离绝缘区域，形成在元件区域中的一对杂质扩散区域以及栅极电极 通过半导体衬底的元件区域中的栅极绝缘膜形成。

公开(公告)号：US20060273330A1

公开(公告)日：2006-12-07

申请号：US11498774

申请日：2006-08-04

申请人： Hajime Nagano ,  Shinichi Nitta ,  Hisato Oyamatsu

发明人： Hajime Nagano ,  Shinichi Nitta ,  Hisato Oyamatsu

IPC分类号： H01L33/00

CPC分类号： H01L27/10894 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer disposed therebetween and exposing part of the semiconductor substrate, removing an exposed region of the semiconductor substrate in a depth direction, and burying a second semiconductor region in the region from which part of the semiconductor substrate has been removed in the depth direction.

摘要翻译： 一种半导体器件制造方法，包括：选择性地去除SOI衬底中的一部分掩埋氧化物层和第一半导体层，所述SOI衬底具有形成于半导体衬底上方的所述掩埋氧化物层的第一半导体层，并且暴露所述半导体衬底的一部分， 区域，并且在半导体衬底的一部分已经在深度方向上被去除的区域中埋入第二半导体区域。

公开(公告)号：US20060258076A1

公开(公告)日：2006-11-16

申请号：US11399655

申请日：2006-04-07

申请人： Ichiro Mizushima ,  Hajime Nagano ,  Yoshio Ozawa ,  Hisataka Meguro ,  Takashi Suzuki

发明人： Ichiro Mizushima ,  Hajime Nagano ,  Yoshio Ozawa ,  Hisataka Meguro ,  Takashi Suzuki

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11521

摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.

摘要翻译： 在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。

公开(公告)号：US20060157697A1

公开(公告)日：2006-07-20

申请号：US11232851

申请日：2005-09-23

申请人： Hajime Nagano

发明人： Hajime Nagano

IPC分类号： H01L21/66 ,  H01L23/58 ,  G01R31/26

CPC分类号： H01L22/20 ,  H01L2224/16 ,  H01L2924/01057 ,  H01L2924/01067

摘要： A system for adjusting a manufacturing condition of an electronic device includes: an inspection tool configured to inspect a plurality of protrusions on a substance layer for manufacturing an electronic device; a height calculation unit configured to calculate each of heights of the protrusions, based on the inspection result; and an adjustment unit configured to adjust a manufacturing condition of the electronic device in order to remove the protrusions, based on the heights.

摘要翻译： 一种用于调整电子设备的制造条件的系统，包括：检查工具，被配置为检查用于制造电子设备的物质层上的多个突起; 高度计算单元，被配置为基于检查结果计算突起的高度; 以及调整单元，被配置为基于高度来调整电子设备的制造条件以便去除突起。

公开(公告)号：US20060131696A1

公开(公告)日：2006-06-22

申请号：US11350027

申请日：2006-02-09

申请人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

发明人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

IPC分类号： H01L29/06 ,  H01L23/02

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S438/974 ,  H01L2924/00

摘要： A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.