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1.发明授权Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate 失效在半导体衬底上形成隔离结构和双极晶体管的方法
公开(公告)号：US5648281A
公开(公告)日：1997-07-15
申请号：US647073
申请日：1996-05-08
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/014 , Y10S438/983
摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种同时形成双极晶体管，相对高压CMOS晶体管，相对低电压CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻器的方法（以下称为“BiCDMOS工艺”），或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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公开(公告)号：US5751054A
公开(公告)日：1998-05-12
申请号：US705910
申请日：1996-08-29
IPC分类号： H01L21/331 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L29/861 , H01L23/62 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L29/0638 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L2924/0002 , Y10S148/009 , Y10S148/085
摘要： A semiconductor structure which includes zener diodes and various combinations of MOS transistors, bipolar transistors and DMOS transistors, all fabricated on the same integrated circuit chip
摘要翻译： 包括齐纳二极管和MOS晶体管，双极晶体管和DMOS晶体管的各种组合的半导体结构，全部制造在相同的集成电路芯片
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公开(公告)号：US5643820A
公开(公告)日：1997-07-01
申请号：US667219
申请日：1996-06-19
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L21/70
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7809 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/014 , Y10S438/983
摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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4.发明授权PMOS transistors with different breakdown voltages formed in the same substrate 失效在同一衬底中形成不同击穿电压的PMOS晶体管
公开(公告)号：US5583061A
公开(公告)日：1996-12-10
申请号：US464435
申请日：1995-06-05
IPC分类号： H01L29/73 , H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/082 , Y10S148/126 , Y10S438/983
摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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5.发明授权MOS transistor having adjusted threshold voltage formed along with other transistors 失效MOS晶体管具有与其它晶体管一起形成的调节阈值电压
公开(公告)号：US5618743A
公开(公告)日：1997-04-08
申请号：US463417
申请日：1995-06-05
IPC分类号： H01L29/73 , H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/082 , Y10S148/126 , Y10S438/983
摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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6.发明授权Method for forming a lateral MOS transistor having lightly doped drain formed along with other transistors in the same substrate 失效用于形成具有轻掺杂漏极的横向MOS晶体管与在同一衬底中的其它晶体管一起形成的方法
公开(公告)号：US5541125A
公开(公告)日：1996-07-30
申请号：US463165
申请日：1995-06-05
IPC分类号： H01L29/73 , H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/082 , Y10S148/126 , Y10S438/983
摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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公开(公告)号：US5559044A
公开(公告)日：1996-09-24
申请号：US323950
申请日：1994-10-17
IPC分类号： H01L29/73 , H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/082 , Y10S148/126 , Y10S438/983
摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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公开(公告)号：US5547880A
公开(公告)日：1996-08-20
申请号：US464978
申请日：1995-06-05
IPC分类号： H01L29/73 , H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L21/04
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/082 , Y10S148/126 , Y10S438/983
摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种同时形成双极晶体管，相对高压CMOS晶体管，相对低电压CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻器的方法（以下称为“BiCDMOS工艺”），或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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9.发明授权
公开(公告)号：US5541123A
公开(公告)日：1996-07-30
申请号：US463647
申请日：1995-06-05
IPC分类号： H01L29/73 , H01L21/331 , H01L21/336 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L21/265
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L29/0847 , H01L29/0878 , Y10S148/082 , Y10S148/126 , Y10S438/983
摘要： A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种方法（以下称为“BiCDMOS工艺”），其同时形成双极型晶体管，相对高压的CMOS晶体管，相对低电压的CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻，或者任何期望的组合 这些，都在同一个集成电路芯片上。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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公开(公告)号：US5416039A
公开(公告)日：1995-05-16
申请号：US225270
申请日：1994-04-08
IPC分类号： H01L21/331 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/10 , H01L29/732 , H01L29/78 , H01L29/861 , H01L21/266
CPC分类号： H01L29/7816 , H01L21/8249 , H01L27/0635 , H01L29/1004 , H01L29/66272 , H01L29/7322 , H01L29/7801 , H01L29/7809 , H01L29/7835 , H01L29/0638 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L2924/0002 , Y10S148/009 , Y10S148/085
摘要： A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
摘要翻译： 公开了一种同时形成高质量互补双极晶体管，相对高电压CMOS晶体管，相对低电压CMOS晶体管，DMOS晶体管，齐纳二极管和薄膜电阻器或这些的任何期望组合的方法，全部在同一集成电路芯片上 。 该工艺使用少量的掩模步骤，形成高性能晶体管结构，并产生高功率的裸片。 还公开了隔离结构，双极晶体管结构，CMOS晶体管结构，DMOS晶体管结构，齐纳二极管结构和薄膜电阻器结构。
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