公开(公告)号：US06717451B1

公开(公告)日：2004-04-06

申请号：US10159089

申请日：2002-05-30

申请人： Hans W. Klein ,  Paul Hildebrant ,  Joey Doernberg ,  Jian Li

发明人： Hans W. Klein ,  Paul Hildebrant ,  Joey Doernberg ,  Jian Li

IPC分类号： H03L500

CPC分类号： H03K5/003 ,  H03F1/301 ,  H03F3/505 ,  H03F2203/5027 ,  H03F2203/5031

摘要： The inventive level shifting circuit shifts an analog input signal by a precise amount. This allows it to be used in precision instrumentation applications where precise signal shifts are critical. It uses a self-biasing feedback circuit to determine the bias current needed to shift an analog signal by a desired amount. The circuit automatically compensates for influences by temperature, supply voltage, and process variations. This circuit also has value as a stand-alone function for other (non-programmable) products.

摘要翻译： 本发明的电平移位电路使模拟输入信号移位精确的量。 这允许将其用于精确的信号偏移至关重要的精密仪器应用中。 它使用自偏置反馈电路来确定将模拟信号移位所需量所需的偏置电流。 该电路自动补偿温度，电源电压和工艺变化的影响。 该电路还具有作为其他（不可编程）产品的独立功能的价值。

公开(公告)号：US06583652B1

公开(公告)日：2003-06-24

申请号：US10159009

申请日：2002-05-30

申请人： Hans W. Klein ,  Jian Li ,  Paul Hildebrant

发明人： Hans W. Klein ,  Jian Li ,  Paul Hildebrant

IPC分类号： H03K522

CPC分类号： H03H11/04 ,  H03F3/45197 ,  H03F2203/45356 ,  H03F2203/45504

摘要： An improved programmable transconductor can be efficiently implemented utilizing a programmable resistor circuit that allows for only a selected portion of the resistor circuit (associated with a desired transconductor gain) to be coupled between summing nodes of the transconductor. Additional switching circuits can be used to reduce gain errors associated with the switches used to implement the aforementioned solution. Additionally, the improved programmable transconductor can be integrated into fully differential programmable analog integrated circuits, thereby enhancing the performance of such integrated circuits.

摘要翻译： 可以使用可允许只有电阻器电路的所选部分（与期望的跨导体增益相关联）耦合在跨导体的求和节点之间来有效地实现改进的可编程跨导体。 可以使用额外的开关电路来减少与用于实现上述解决方案的开关相关联的增益误差。 此外，改进的可编程跨导体可以集成到全差分可编程模拟集成电路中，从而提高这种集成电路的性能。

公开(公告)号：US06806771B1

公开(公告)日：2004-10-19

申请号：US10159681

申请日：2002-05-31

申请人： Paul Hildebrant ,  Jian Li ,  Hans W. Klein

发明人： Paul Hildebrant ,  Jian Li ,  Hans W. Klein

IPC分类号： H03G310

CPC分类号： H03F3/45475 ,  H03F1/3211 ,  H03F3/3022 ,  H03F3/45183 ,  H03F3/45748 ,  H03F3/45973 ,  H03F2200/261 ,  H03F2200/78 ,  H03F2203/45458 ,  H03F2203/45526 ,  H03G3/001

摘要： An output block for an in-system programmable analog integrated circuit. The output block features an output amplifier that accepts a differential current-mode input signal and provides a single-ended output voltage. The output amplifier is also selectably operable as a linear amplifier, an integrator or a comparator. The output block also includes a common-mode feedback circuit (CMFB), an analog trim circuit (OATRM), a CLAMP circuit, and an offset calibration circuit (CLDAC), all coupled to the differential input of the output amplifier. The CMFB exhibits bandwidth comparable to that of the output amplifier and a drive capability that enables the differential-input to single-ended output conversion. The CLAMP is connected to the differential input in the comparator mode in order to avoid slow recovery from an overdrive condition. The OATRM forces a difference current into the differential input that compensates for a (gain independent) offset voltage that results from various mismatches. The CLDAC uses a digital-to-analog converter (DAC) to perform offset calibration at the differential input of the output amplifier. In addition, the output block is configured to be operational in a number of user-selectable modes, including, in one embodiment, one or more of: a linear (NORM) mode, a comparator (COMP) mode, and an integrator (INT) mode. An amplifier in the output block is variously reconfigured to achieve the selected mode of operation. Also, the output block accommodates an autocalibration (CAL) technique by clamping the single-ended output stage and balancing, through operation of the CLDAC, signals at an input node and at an interstage node of the amplifier.

摘要翻译： 用于在系统可编程模拟集成电路的输出块。 输出模块具有输出放大器，可接受差分电流模式输入信号，并提供单端输出电压。 输出放大器也可选择可操作为线性放大器，积分器或比较器。 输出块还包括共模反馈电路（CMFB），模拟微调电路（OATRM），钳位电路和偏移校准电路（CLDAC），全部耦合到输出放大器的差分输入。 CMFB具有与输出放大器的带宽相当的带宽，以及使差分输入能够实现单端输出转换的驱动能力。 CLAMP在比较器模式下连接到差分输入，以避免从过驱动条件恢复缓慢。 OATRM将差分电流强制为差分输入，补偿由各种不匹配产生的（增益无关）偏移电压。 CLDAC使用数模转换器（DAC）在输出放大器的差分输入端执行偏移校准。 此外，输出块被配置为可在多个用户可选模式下操作，包括在一个实施例中，一个或多个：线性（NORM）模式，比较器（COMP）模式和积分器（INT ）模式。 输出块中的放大器被不同地重新配置以实现所选择的操作模式。 此外，输出块通过钳位单端输出级并通过CLDAC的操作在放大器的输入节点和级间节点处的信号进行平衡来适应自动校准（CAL）技术。

公开(公告)号：US06362684B1

公开(公告)日：2002-03-26

申请号：US09506180

申请日：2000-02-17

申请人： Hans W. Klein ,  Jian Li ,  Yaohua Yang

发明人： Hans W. Klein ,  Jian Li ,  Yaohua Yang

IPC分类号： H03G310

CPC分类号： H03G1/0088 ,  H03G3/001

摘要： Provided is an amplifier circuit and method of using the same that features an adjustable resistor network to enable varying the operational characteristics of an amplifier. The resistor network includes primary resistors connected in series with a plurality of adjustment resistors connected to the output of an operational amplifier. A switching network is connected between the resistor network and the input of the operational amplifier. The switching network enables selectively varying the input and feedback resistance of the amplifier circuit to obtain a desired differential gain, while minimizing common-mode gain.

摘要翻译： 提供了一种放大器电路及其使用方法，其特征在于具有可调电阻器网络，以能够改变放大器的操作特性。 电阻网络包括与连接到运算放大器的输出的多个调节电阻串联连接的主电阻器。 开关网络连接在电阻网络和运算放大器的输入端之间。 开关网络能够选择性地改变放大器电路的输入和反馈电阻以获得期望的差分增益，同时最小化共模增益。

公开(公告)号：US08384467B1

公开(公告)日：2013-02-26

申请号：US13534299

申请日：2012-06-27

申请人： Daniel O'Keeffe ,  Kevin Gallagher ,  Denis Ellis ,  Hans W. Klein

发明人： Daniel O'Keeffe ,  Kevin Gallagher ,  Denis Ellis ,  Hans W. Klein

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/073

摘要： An apparatus includes a charge pump array including multiple charge pump cells. The charge pump array is configurable into a first arrangement of the charge pump cells coupled in series or a second arrangement of the charge pump cells coupled in parallel. The apparatus can include reconfiguration circuitry configured to select the first arrangement of the charge pump cells or the second arrangement of the charge pump cells. The charge pump array is configured to alter a voltage level of a signal based, at least in part, on the selected arrangement of the charge pump cells.

摘要翻译： 一种装置包括一个包括多个电荷泵电池的电荷泵阵列。 电荷泵阵列可配置成串联耦合的电荷泵单元的第一布置或并联耦合的电荷泵单元的第二布置。 该装置可以包括被配置为选择电荷泵单元的第一布置或电荷泵单元的第二布置的重新配置电路。 电荷泵阵列被配置为至少部分地基于所选择的电荷泵单元的布置来改变信号的电压电平。

公开(公告)号：US20120256869A1

公开(公告)日：2012-10-11

申请号：US13249514

申请日：2011-09-30

申请人： Paul Walsh ,  Hans W. Klein ,  Keith O'Donoghue ,  Erik Anderson ,  Erhan Hancioglu ,  Gajender Rohilla

发明人： Paul Walsh ,  Hans W. Klein ,  Keith O'Donoghue ,  Erik Anderson ,  Erhan Hancioglu ,  Gajender Rohilla

IPC分类号： G06F3/044 ,  G06G7/184 ,  G06G7/18

CPC分类号： G06F3/044 ,  G01R27/2605 ,  G06F3/03547 ,  G06F3/041 ,  G06F3/0416 ,  G06F3/0418 ,  G06F2203/04103 ,  G06F2203/04111

摘要： An active integrator for sensing capacitance of a touch sense array is disclosed. The active integrator is configured to receive from the touch sense array a response signal having a positive portion and a negative portion. The response signal is representative of a presence or an absence of a conductive object on the touch sense array. The active integrator is configured to continuously integrate the response signal.

摘要翻译： 公开了一种用于感测触摸感测阵列的电容的有源积分器。 有源积分器被配置为从触摸感测阵列接收具有正部分和负部分的响应信号。 响应信号代表触摸感测阵列上导电物体的存在或不存在。 有源积分器被配置为连续地对响应信号进行积分。

公开(公告)号：US07111183B1

公开(公告)日：2006-09-19

申请号：US10269804

申请日：2002-10-10

申请人： Hans W. Klein ,  Frederic N. F. Deboes ,  Douglas C. Morse

发明人： Hans W. Klein ,  Frederic N. F. Deboes ,  Douglas C. Morse

IPC分类号： G06F1/24 ,  G06F1/26

CPC分类号： G06F1/26

摘要： Power-sequencing controllers are connected to allow more complex power sequencing and/or larger numbers of voltage supplies to be monitored than with a single controller. Power-on-reset (POR) output signals from the “slave” controllers are connected by a wired-OR, and the composite output is used as a reset signal or indicator signal by the “master” controller. An output from the master controller coupled to the composite input signal is connected with the {overscore (POR)} output of the master controller by a wired-OR, and this composite signal is coupled to the reset terminals of the slave controllers. Connecting controllers in a master/slave configuration allows prevents any of the slave devices from starting until all the devices have been released, resulting in synchronous processing of subsequent signals and events.

摘要翻译： 电源排序控制器被连接以允许监视比与单个控制器相比更复杂的电源排序和/或更大数量的电压源。 来自“从”控制器的上电复位（POR）输出信号通过有线或并联连接，复合输出由“主”控制器用作复位信号或指示信号。 耦合到复合输入信号的主控制器的输出端通过线 - 或（与主控制器的POR输出相连），并将该复合信号耦合到从控制器的复位端，将控制器连接到 主/从配置允许防止任何从设备启动，直到所有设备已经释放，导致后续信号和事件的同步处理。

公开(公告)号：US06885227B2

公开(公告)日：2005-04-26

申请号：US10629221

申请日：2003-07-29

申请人： Om P. Agrawal ,  Hans W. Klein ,  Geoffrey R. Rickard ,  Harald J. Weller

发明人： Om P. Agrawal ,  Hans W. Klein ,  Geoffrey R. Rickard ,  Harald J. Weller

IPC分类号： H03L7/089 ,  H03L7/099 ,  H03L7/18 ,  H03L7/06

CPC分类号： H03L7/0891 ,  H03L7/0995 ,  H03L7/0996 ,  H03L7/18

摘要： Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable and includes a flexible skew control architecture. The clock generator chip may also provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

公开(公告)号：US5581536A

公开(公告)日：1996-12-03

申请号：US484431

申请日：1995-06-07

申请人： Hans W. Klein ,  Sriram Narayan

发明人： Hans W. Klein ,  Sriram Narayan

IPC分类号： G11B5/596 ,  G11B7/09 ,  G11B15/60 ,  G11B17/34 ,  G11B21/10 ,  H03K5/1532 ,  G11B7/00

CPC分类号： G11B7/0901 ,  G11B21/10 ,  G11B5/59611 ,  H03K5/1532 ,  G11B15/602 ,  G11B17/34 ,  G11B7/0941

摘要： A circuit for detecting when peaks occur in an amplitude modulated electrical signal, and for measuring in real time the amplitudes of the detected peaks. The circuit delays the input signal a short time, and then notes when the input signal and its delayed version have the same amplitude, thereby to detect when a peak has occurred. The amplitude of the peak is then measured. This circuit and technique have particular advantages when used as part of a servo control system that positions a read/write head to accurately follow moving tracks of recorded data on magnetic tape, magnetic disks, optical disks, and the like.

摘要翻译： 用于检测在调幅电信号中何时发生峰值的电路，并用于实时测量检测到的峰值的振幅。 该电路在短时间内延迟输入信号，然后在输入信号及其延迟版本具有相同幅度时注意，从而检测峰值何时发生。 然后测量峰的振幅。 当用作伺服控制系统的一部分时，该电路和技术具有特别的优点，该伺服控制系统将读/写头准确地跟踪在磁带，磁盘，光盘等上的记录数据的移动轨迹。

公开(公告)号：US06901572B1

公开(公告)日：2005-05-31

申请号：US10272582

申请日：2002-10-15

申请人： Paul R. Dougherty ,  Srirama Chandra ,  Hans W. Klein

发明人： Paul R. Dougherty ,  Srirama Chandra ,  Hans W. Klein

IPC分类号： G06F17/50 ,  H03K19/00 ,  G06F1/26

CPC分类号： G06F17/5054

摘要： A programming technique for a programmable logic device (PLD) is disclosed wherein the programmed PLD controls a circuit's behavior according to a desired circuit behavior implementation. A user constructs a program, wherein the program comprises instructions defining inputs, outputs, and conditional branching for an abstract state sequencer that implements the desired circuit behavior. The programming technique then translates the states and resources for the abstract state sequencer into HDL source code, which in turn may be translated into a programming bit pattern for the PLD.

摘要翻译： 公开了一种用于可编程逻辑器件（PLD）的编程技术，其中编程的PLD根据期望的电路行为实现来控制电路的行为。 用户构建程序，其中程序包括定义用于实现所需电路行为的抽象状态定序器的输入，输出和条件分支的指令。 然后，编程技术将抽象状态定序器的状态和资源转换为HDL源代码，然后将其转换为PLD的编程位模式。