公开(公告)号：US07019554B2

公开(公告)日：2006-03-28

申请号：US10727106

申请日：2003-12-03

申请人： Oliver Kiehl ,  Hans-Heinrich Viehmann

发明人： Oliver Kiehl ,  Hans-Heinrich Viehmann

IPC分类号： H03K19/003

CPC分类号： H04L25/0298

摘要： An integrated circuit includes at least one main circuit 313 operable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuit 301 has first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.

摘要翻译： 集成电路包括至少一个可操作以执行一个或多个功能的主电路313。 至少一个终端节点DQ接收或发送操作信号。 有源终端电路301具有串联耦合在第一源电位的Vdd节点和第二源极电位的Vss节点之间的相反类型的第一和第二晶体管。 至少一个终端节点耦合到第一和第二晶体管之间的公共节点。 控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处呈现受控阻抗。 或者，控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处提供钳位功能。

公开(公告)号：US20050122130A1

公开(公告)日：2005-06-09

申请号：US10727106

申请日：2003-12-03

申请人： Oliver Kiehl ,  Hans-Heinrich Viehmann

发明人： Oliver Kiehl ,  Hans-Heinrich Viehmann

IPC分类号： H03K19/003 ,  H04L25/02

CPC分类号： H04L25/0298

摘要： An integrated circuit includes at least one main circuit 313 operable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuit 301 has first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.

摘要翻译： 集成电路包括至少一个可操作以执行一个或多个功能的主电路313。 至少一个终端节点DQ接收或发送操作信号。 有源终端电路301具有串联耦合在第一源电位的Vdd节点和第二源极电位的Vss节点之间的相反类型的第一和第二晶体管。 至少一个终端节点耦合到第一和第二晶体管之间的公共节点。 控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处呈现受控阻抗。 或者，控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处提供钳位功能。

公开(公告)号：US20050012519A1

公开(公告)日：2005-01-20

申请号：US10620989

申请日：2003-07-16

申请人： Hans-Heinrich Viehmann ,  Oliver Kiehl

发明人： Hans-Heinrich Viehmann ,  Oliver Kiehl

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0298

摘要： An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.

摘要翻译： 一种集成电路，包括：可操作以执行一个或多个功能的至少一个主电路，并且包括用于接收或发送操作信号的至少一个I / O节点; 有源终端电路具有相同类型的第一和第二MOSFET串联耦合跨越第一源电位的Vdd节点和第二源电位的Vss节点，所述至少一个I / O节点耦合到公共节点之间 第一和第二MOSFET; 以及控制电路，其可操作以偏置第一和第二MOSFET，使得它们在公共节点处呈现受控阻抗。

公开(公告)号：US06937058B2

公开(公告)日：2005-08-30

申请号：US10620989

申请日：2003-07-16

申请人： Hans-Heinrich Viehmann ,  Oliver Kiehl

发明人： Hans-Heinrich Viehmann ,  Oliver Kiehl

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0298

摘要： An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.

公开(公告)号：US20080313494A1

公开(公告)日：2008-12-18

申请号：US11763593

申请日：2007-06-15

申请人： Klaus Hummler ,  Jong Hoon Oh ,  Wayne Frederick Ellis ,  Jung Pill Kim ,  Oliver Kiehl ,  Josef Schnell ,  Octavian Beldiman ,  Lee Ward Collins

发明人： Klaus Hummler ,  Jong Hoon Oh ,  Wayne Frederick Ellis ,  Jung Pill Kim ,  Oliver Kiehl ,  Josef Schnell ,  Octavian Beldiman ,  Lee Ward Collins

IPC分类号： G06F11/16

CPC分类号： G11C29/02 ,  G11C7/1039 ,  G11C11/401 ,  G11C11/406 ,  G11C29/028 ,  G11C29/50016 ,  G11C2211/4062 ,  G11C2211/4065

摘要： A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.

摘要翻译： 刷新调度器被配置为根据多个刷新间隔刷新存储器设备的存储单元。 响应于刷新错误确定各种刷新间隔。

公开(公告)号：US20080189480A1

公开(公告)日：2008-08-07

申请号：US11701006

申请日：2007-02-01

申请人： Jung Pill Kim ,  Jong-Hoon Oh ,  Oliver Kiehl ,  Josef Schnell ,  Klaus Hummler ,  Wayne Ellis ,  Octavian Beldiman ,  Lee Collins

发明人： Jung Pill Kim ,  Jong-Hoon Oh ,  Oliver Kiehl ,  Josef Schnell ,  Klaus Hummler ,  Wayne Ellis ,  Octavian Beldiman ,  Lee Collins

IPC分类号： G06F12/00

CPC分类号： G11C5/04 ,  G11C5/063 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/181 ,  H01L2224/0401

摘要： A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.

摘要翻译： 存储器包括第一宏芯片，脊芯片和公共基板。 公共基板被配置为在第一宏芯片和脊芯片之间传递信号。 第一个宏芯片，脊椎芯片和公共基板提供了一个记忆。

公开(公告)号：US07321628B2

公开(公告)日：2008-01-22

申请号：US10674859

申请日：2003-09-30

申请人： Oliver Kiehl

发明人： Oliver Kiehl

IPC分类号： H04L27/00

CPC分类号： H04L25/4915

摘要： System and method for reducing power consumption and noise in a transmission system with an asymmetrically terminated transmission line. A preferred embodiment comprises encoding data words to reduce the number of times a given state appears in a code word. The preferred embodiment comprises counting the number of times a given state appears in a data word. If the count is greater than half of the total number of bits in the data word, then the data word is inverted and a weight bit can be set to the given state. If the count is less than (or equal to) half of the total number of bits, then the data word may be unchanged and the weight bit can be set to the inverse of the given state. The code word can be generated by appending the weight bit to the data word.

摘要翻译： 具有不对称端接传输线的传输系统中降低功耗和噪声的系统和方法。 优选实施例包括编码数据字以减少给定状态在码字中出现的次数。 优选实施例包括对给定状态在数据字中出现的次数进行计数。 如果计数大于数据字中总位数的一半，则数据字被反转，并且可以将权重位设置为给定状态。 如果计数小于（或等于）总位数的一半，则数据字可以不变，并且权重位可以被设置为给定状态的倒数。 可以通过将权重位附加到数据字来生成代码字。

公开(公告)号：US07215595B2

公开(公告)日：2007-05-08

申请号：US10967899

申请日：2004-10-18

申请人： Oliver Kiehl

发明人： Oliver Kiehl

IPC分类号： G11C8/18

CPC分类号： G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C11/4094 ,  G11C2207/005

摘要： A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.

摘要翻译： 存储器件包括一对补充位线，包括第一位线和第二位线。 位线预充电块耦合在第一位线和第二位线之间。 读出放大器耦合到第一位线和第二位线，读出放大器预充电块耦合到读出放大器。 读出放大器预充电块可以独立于位线预充电块来激活。 隔离块耦合在一对互补位线和一侧的位线预充电块和另一侧的读出放大器和读出放大器预充电块之间。

公开(公告)号：US06730989B1

公开(公告)日：2004-05-04

申请号：US09596130

申请日：2000-06-16

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L23544

CPC分类号： H01L23/5382 ,  H01L23/50 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US06294940B1

公开(公告)日：2001-09-25

申请号：US09598349

申请日：2000-06-21

申请人： Oliver Kiehl

发明人： Oliver Kiehl

IPC分类号： H03K300

CPC分类号： H03K5/1534 ,  G06F1/10 ,  H03K5/00006

摘要： A clock circuit, in accordance with the present invention, includes a first circuit stage for providing a first output signal and a second output signal. The first circuit stage includes inputs for clock signals. A switch is coupled to the first stage for switching an output polarity by selecting one of the first output signal and the second output signal generated by the first circuit stage in accordance with a control signal. A second circuit stage is coupled to the first circuit stage through the switch. The second circuit stage for shaping the first and second output signals input thereto from the switch. The second circuit stage includes an output for outputting clock pulses based on the first and second output signals. The control signal is generated from the clock pulses.

摘要翻译： 根据本发明的时钟电路包括用于提供第一输出信号和第二输出信号的第一电路级。 第一个电路级包括时钟信号的输入。 开关通过根据控制信号选择由第一电路级产生的第一输出信号和第二输出信号之一来耦合到第一级用于切换输出极性。 第二电路级通过开关耦合到第一电路级。 用于对从开关输入的第一和第二输出信号进行整形的第二电路级。 第二电路级包括用于基于第一和第二输出信号输出时钟脉冲的输出。 控制信号由时钟脉冲产生。