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1.发明申请公开(公告)号：US20050157546A1
公开(公告)日：2005-07-21
申请号：US10758449
申请日：2004-01-15
CPC分类号： G11C11/16
摘要： The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.
摘要翻译： 在开始磁存储单元的写操作之前，MRAM器件的写入路径被预充电，增加了写操作的速度并减小了写周期时间。 参考线是预充电的，可以更好地控制字线和位线写入脉冲，从而缩短上升时间。 预充电时间可以隐藏在地址解码时间或冗余评估时间内。 本文还描述了用于全局参考电流发生器的电路设计。 还公开了一种快速接通电路，其增加对参考线预充电的速度。
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2.发明授权Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption 有权用于将差分模式信号转换成具有降低待机电流消耗的单端信号的电路公开(公告)号：US06819142B2
公开(公告)日：2004-11-16
申请号：US10387733
申请日：2003-03-13
IPC分类号： H03K1920
CPC分类号： H03K19/018528 , H03K19/0016
摘要： An apparatus for converting a differential mode signal into a single ended signal with reduced power consumption. A preferred embodiment comprises a single ended converter (for example, a single ended converter 505) and an output transistor (for example, output transistor 524) that when the single ended converter 505 is in standby may pull the output of the single ended converter 505 to a known logic state (such as high logic or low logic). A single ended buffer (inverting or non-inverting) may be used for output signal compatibility conversion.
摘要翻译： 一种用于将差分模式信号转换成具有降低的功耗的单端信号的装置。 优选实施例包括单端转换器（例如，单端转换器505）和输出晶体管（例如，输出晶体管524），当单端转换器505处于待机状态时，可以将单端转换器505的输出 到一个已知的逻辑状态（如高逻辑或低逻辑）。 单端缓冲器（反相或非反相）可用于输出信号兼容性转换。
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3.发明授权公开(公告)号：US07057924B2
公开(公告)日：2006-06-06
申请号：US10758449
申请日：2004-01-15
IPC分类号： G11C11/14
CPC分类号： G11C11/16
摘要： The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.
摘要翻译： 在开始磁存储单元的写入操作之前，MRAM器件的写入路径被预充电，增加写入操作的速度并减小写入周期时间。 参考线是预充电的，可以更好地控制字线和位线写入脉冲，从而缩短上升时间。 预充电时间可以隐藏在地址解码时间或冗余评估时间内。 本文还描述了用于全局参考电流发生器的电路设计。 还公开了一种快速接通电路，其增加对参考线预充电的速度。
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公开(公告)号：US06930915B2
公开(公告)日：2005-08-16
申请号：US10465003
申请日：2003-06-19
CPC分类号： G11C11/15
摘要： A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.
摘要翻译： 一种在交叉点磁存储器阵列和交叉点磁存储器件结构中存储信息的方法。 在写入操作期间，跨越磁隧道结（MTJ）的电压降最小化，以防止损坏阵列的MTJ。 选择的MTJ，未选择的MTJ或两者的电压降在写操作期间被最小化，减少了MTJ的压力，减少了泄漏电流，降低了功耗并增加了写入裕度。
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5.发明授权公开(公告)号：US06853229B2
公开(公告)日：2005-02-08
申请号：US10391850
申请日：2003-03-19
CPC分类号： H03K5/151 , H03K3/0375
摘要： An apparatus for transforming single ended signals into differential mode signals. A preferred embodiment comprises an inverter (for example, inverter 505) and a pair of latches (for example, latches 510 and 520). One latch has as its input an input signal to be converted and the other latch has as its input an inverse of the input signal. The latches maybe clocked by a differential mode clock and remove a timing mismatch between the input signal and its inverse that is incurred via the inverter. The latch outputs are then provided to a differential mode buffer to perform signal voltage and current compatibility transformations.
摘要翻译： 一种用于将单端信号变换为差模信号的装置。 优选实施例包括逆变器（例如，反相器505）和一对锁存器（例如，锁存器510和520）。 一个锁存器具有作为其输入的输入信号，并且另一个锁存器具有作为输入信号的反相的输入信号。 锁存器可以由差分模式时钟计时，并消除通过变频器产生的输入信号与其反相之间的定时失配。 然后将锁存器输出提供给差分模式缓冲器，以执行信号电压和电流兼容性转换。
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6.发明授权公开(公告)号：US06825707B2
公开(公告)日：2004-11-30
申请号：US10384860
申请日：2003-03-10
IPC分类号： H03K1762
CPC分类号： H03K5/133 , H03K2005/00026 , H03K2005/00156 , H03K2005/00208
摘要： An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example, multiplexer 210) in both buffered (via a buffer (for example, buffer 205)) and unbuffered form. A control signal of the multiplexer may be used to select from either the buffered or unbuffered input signals. By using a control signal at an intermediate value (somewhere in between values that selects the buffered or unbuffered input signals), the multiplexer may then combine the buffered and unbuffered input signals in proportion with the value of the control signal and imparts a delay upon the input signal that may be in between the delay imparted by the buffer.
摘要翻译： 一种用于电流模式逻辑可变延迟元件的装置。 优选实施例包括提供给缓冲（经由缓冲器（例如，缓冲器205））和非缓冲形式的多路复用器（例如，多路复用器210）的输入信号。 可以使用多路复用器的控制信号来从缓冲或非缓冲输入信号中进行选择。 通过使用中间值（选择缓冲或非缓冲输入信号的值之间的某处）的控制信号，多路复用器然后可以将缓冲和非缓冲输入信号与控制信号的值成比例地组合，并且在 可能在由缓冲器赋予的延迟之间的输入信号。
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7.发明授权CML (current mode logic) OCD (off chip driver)—ODT (on die termination) circuit for bidirectional data transmission 有权CML（电流模式逻辑）OCD（芯片外驱动器）-ODT（芯片端接）电路，用于双向数据传输公开(公告)号：US06847225B2
公开(公告)日：2005-01-25
申请号：US10394779
申请日：2003-03-21
IPC分类号： H03K19/0185 , H04L25/02 , H03K17/16 , H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H04L25/0278 , H03K19/018592 , H04L25/0272 , H04L25/0282 , H04L25/0294
摘要： An apparatus for use as both an off chip driver (OCD) and an on die termination (ODT) circuits. A preferred embodiment comprises a control circuit (for example, control circuit 305) coupled to a dual function OCD/ODT circuit (for example, OCD/ODT circuit 330) with an enable line coupled to the control circuit. The control circuit may be used to selectively choose OCD and ODT functionality based on a value on the enable line. With the control circuit choosing OCD, the dual function OCD/ODT circuit functions as an OCD circuit, placing signals provided through the control circuit onto a transmission line. With the control circuit choosing ODT, the dual function OCD/ODT circuit becomes terminating resistors for incoming signals on a transmission line. The use of a single circuit for both OCD and ODT functions can save both integrated circuit real-estate and implementation costs due to a reduction in use of circuit elements.
摘要翻译： 用作片外驱动器（OCD）和芯片上端接（ODT）电路的装置。 优选实施例包括耦合到耦合到控制电路的使能线的双功能OCD / ODT电路（例如，OCD / ODT电路330）的控制电路（例如，控制电路305）。 控制电路可以用于基于使能线上的值来选择OCD和ODT功能。 通过选择OCD的控制电路，双功能OCD / ODT电路用作OCD电路，将通过控制电路提供的信号放置在传输线上。 通过控制电路选择ODT，双功能OCD / ODT电路成为传输线上输入信号的终端电阻。 对于OCD和ODT功能，单电路的使用可以节省电路元件的使用减少集成电路的不动产和实施成本。
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8.发明授权Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module 有权集成电路，集成电路的操作方法，集成电路的制造方法，存储器模块，可堆叠存储器模块公开(公告)号：US07433253B2
公开(公告)日：2008-10-07
申请号：US11768508
申请日：2007-06-26
CPC分类号： G11C7/067 , G11C5/02 , G11C5/04 , G11C11/1673 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C2013/0054 , G11C2207/063 , G11C2213/71 , G11C2213/79
摘要： An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.
摘要翻译： 集成电路具有电流检测放大器，其包括具有第一输入，第二输入和输出的电压比较器; 耦合在电压比较器的第一输入端和第一输入信号节点之间的第一钳位装置，耦合在电压比较器的第二输入端和第二输入信号节点之间的第二钳位装置，具有第一侧和第二 电流镜第一侧包括耦合在电压源和第一钳位装置之间的第一晶体管和电流镜第二侧，其包括耦合在电压源和第二钳位装置之间的第二晶体管，以及感测方案，包括主动平衡 耦合到第二晶体管的源极和漏极的电容。
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公开(公告)号：US20060104136A1
公开(公告)日：2006-05-18
申请号：US10988787
申请日：2004-11-15
IPC分类号： G11C7/02
CPC分类号： G11C5/145 , G11C7/06 , G11C7/12 , G11C11/16 , G11C2207/063
摘要： A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.
摘要翻译： 包括钳位装置和电流镜的电流检测放大器被配置为使用位线升压电路感测MTJ存储器单元的电阻，以缩短寄生电路电容的充电时间。 位线升压电路包括耦合到参考电压的源极跟随器和耦合到另一个电压源的开关。 在感测存储单元的电阻的初始时段期间，该开关能够导通。 位线升压电路中的源极跟随器被配置为将输入信号的电压钳位在与钳位装置基本相同的电平上，并提供额外的电流以缩短对寄生电容充电的周期。 所得到的电流检测放大器可用于实现具有快速可靠的读取时间和低制造成本的存储器件。
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公开(公告)号：US07019554B2
公开(公告)日：2006-03-28
申请号：US10727106
申请日：2003-12-03
IPC分类号： H03K19/003
CPC分类号： H04L25/0298
摘要： An integrated circuit includes at least one main circuit 313 operable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuit 301 has first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.
摘要翻译： 集成电路包括至少一个可操作以执行一个或多个功能的主电路313。 至少一个终端节点DQ接收或发送操作信号。 有源终端电路301具有串联耦合在第一源电位的Vdd节点和第二源极电位的Vss节点之间的相反类型的第一和第二晶体管。 至少一个终端节点耦合到第一和第二晶体管之间的公共节点。 控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处呈现受控阻抗。 或者，控制电路操作以偏置第一和第二晶体管，使得它们在公共节点处提供钳位功能。
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