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公开(公告)号：US20050050261A1
公开(公告)日：2005-03-03
申请号：US10650458
申请日：2003-08-27
申请人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
发明人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
CPC分类号： G11C8/12 , G06F12/0893 , G06F2212/2022 , G06F2212/2024 , G11C16/10 , G11C2207/2245
摘要： A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.
摘要翻译： 数据存储装置包括控制器，FeRAM存储器单元和具有比FeRAM存储器单元高得多的数据存储容量的闪存单元。 最初，当数据存储装置接收到数据时，控制器将其存储在FeRAM存储单元中。 这可以非常快速地完成，因为FeRAM器件具有高写入速率。 随后，控制器将数据传送到闪存单元。 因此，数据存储设备结合了FeRAM器件的高存储容量和闪存器件的高存储容量。
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公开(公告)号：US06885597B2
公开(公告)日：2005-04-26
申请号：US10065011
申请日：2002-09-10
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/1204 , G11C2029/5004
摘要： A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
摘要翻译： 公开了一种用于在存储器访问期间测试差分读取信号的测试电路。 测试电路耦合到一对位线。 在读访问期间，所选存储单元在位线上产生差分读信号。 当测试电路被激活时，差分读取信号的幅度是变化的。 这使得能够容易地测试例如存储器IC中的读取信号余量。
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3.发明申请Signal margin test mode for FeRAM with ferroelectric reference capacitor 审中-公开具有铁电参考电容的FeRAM的信号余量测试模式公开(公告)号：US20050063213A1
公开(公告)日：2005-03-24
申请号：US10665402
申请日：2003-09-18
申请人： Michael Jacob , Thomas Roehr , Hans-Oliver Joachim
发明人： Michael Jacob , Thomas Roehr , Hans-Oliver Joachim
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： The present invention provides a semiconductor memory test mode configuration. A first capacitor stores digital data and connects a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier is connected to the first and reference bit-lines and measures a differential read signal on the first and reference bit-lines. A charge path reduces the differential read signal to determine the signal margin of the semiconductor memory.
摘要翻译： 本发明提供半导体存储器测试模式配置。 第一电容器存储数字数据，并且通过第一选择晶体管将单元板线连接到第一位线。 第一个选择晶体管通过与字线的连接来激活。 至少一个参考电容器为参考位线提供参考电压。 读出放大器连接到第一和参考位线，并测量第一和参考位线上的差分读取信号。 充电路径减小差分读取信号以确定半导体存储器的信号余量。
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公开(公告)号：US06999887B2
公开(公告)日：2006-02-14
申请号：US10636369
申请日：2003-08-06
IPC分类号： G06F3/06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译： 公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。 在写入周期期间，首先将数据写入存储单元。 在第一读取周期期间从存储器单元读取低电平信号。 比较低信号和低参考信号。 比较结果存储在第一存储寄存器中。 在写入周期期间，第二个数据被写入存储单元。 在第二读取周期期间，从存储器单元读取高电平信号。 在高电平信号和高参考信号之间进行比较。 比较结果存储在第二存储寄存器中。 比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出 高参考信号。
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5.发明授权2T2C signal margin test mode using a defined charge exchange between BL and/BL 失效2T2C信号余量测试模式，使用BL和/ BL之间定义的电荷交换公开(公告)号：US06876590B2
公开(公告)日：2005-04-05
申请号：US10301548
申请日：2002-11-20
申请人： Hans-Oliver Joachim , Michael Jacob , Nobert Rehm
发明人： Hans-Oliver Joachim , Michael Jacob , Nobert Rehm
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.
摘要翻译： 本发明提供了一种测试模式部分，用于促进用于信号余量的最坏情况产品测试序列，以确保整个组件寿命期间的全部产品功能，从而考虑所有老化效应。 半导体存储器测试模式配置包括用于存储数字数据并通过第一选择晶体管将单元板线连接到第一位线的第一电容器。 通过连接到字线而激活的第一选择晶体管。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 通过与字线的连接激活第二选择晶体管。 读出放大器连接到第一和第二位线，并测量第一和第二位线上的差分读取信号。 第三晶体管在第一和第二位线之间传输电荷，以减少差分读取信号。
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6.发明申请Reference circuit implemented to reduce the degradation of reference capacitors providing reference voltages for 1T1C FeRAM devices 审中-公开实现参考电路，以减少为1T1C FeRAM器件提供参考电压的参考电容的劣化公开(公告)号：US20050063212A1
公开(公告)日：2005-03-24
申请号：US10665401
申请日：2003-09-18
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： A semiconductor memory comprises a first capacitor for storing digital data connecting a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier connected to the first and reference bit-lines measures a differential read signal on the first and reference bit-lines. A toggle flip flop alternately changes the polarization of charge stored on the reference capacitors.
摘要翻译： 半导体存储器包括用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据的第一电容器。 第一个选择晶体管通过与字线的连接来激活。 至少一个参考电容器为参考位线提供参考电压。 连接到第一和参考位线的读出放大器测量第一和参考位线上的差分读取信号。 触发触发器交替地改变存储在参考电容器上的电荷的极化。
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公开(公告)号：US20050033541A1
公开(公告)日：2005-02-10
申请号：US10636369
申请日：2003-08-06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译： 公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。 在写入周期期间，首先将数据写入存储单元。 在第一读取周期期间从存储器单元读取低电平信号。 比较低信号和低参考信号。 比较结果存储在第一存储寄存器中。 在写入周期期间，第二个数据被写入存储单元。 在第二读取周期期间，从存储器单元读取高电平信号。 在高电平信号和高参考信号之间进行比较。 比较结果存储在第二存储寄存器中。 比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出 高参考信号。
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公开(公告)号：US06731554B1
公开(公告)日：2004-05-04
申请号：US10301546
申请日：2002-11-20
申请人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
发明人： Michael Jacob , Joerg Wohlfahrt , Thomas Roehr , Nobert Rehm
IPC分类号： G11C2900
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data connecting a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines A resistor is connected to one or both of the bit lines through transistors for adding or reducing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译： 本发明提供了一种测试模式部分，用于促进针对信号余量的最坏情况产品测试序列，以确保在整个组件寿命期间的全部产品功能，同时考虑所有的老化效应。 半导体存储器测试模式配置包括：第一电容器，用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据。 第一个选择晶体管通过与字线的连接来激活。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 通过与字线的连接激活第二选择晶体管。 读出放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。电阻器通过晶体管连接到一个或两个位线，用于增加或减少第一和第二位线上的电荷量 当第三晶体管导通时减小差分读取信号的位线。
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公开(公告)号：US06724026B2
公开(公告)日：2004-04-20
申请号：US10065123
申请日：2002-09-19
申请人： Michael Jacob , Andreas Hilliger , Thomas Roehr , Susumo Shuto , Toru Ozaki
发明人： Michael Jacob , Andreas Hilliger , Thomas Roehr , Susumo Shuto , Toru Ozaki
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： An improved cell design for series memory architecture is disclosed. The improved cell design facilitates the formation of capacitors using a single etch process instead of two, as conventionally required. In one embodiment, each capacitor of a capacitor pair is provided with at least one plug contacting a common diffusion region of two adjacent cell transistors. In another embodiment, a large plug with sufficient overlap to the bottom electrodes of pair of capacitors is used.
摘要翻译： 公开了用于串行存储器架构的改进的单元设计。 改进的电池设计有助于使用单一蚀刻工艺形成电容器，而不是如常规要求的那样。 在一个实施例中，电容器对的每个电容器设置有接触两个相邻单元晶体管的公共扩散区域的至少一个插头。 在另一个实施例中，使用与一对电容器的底部电极具有足够重叠的大插头。
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公开(公告)号：US06950328B2
公开(公告)日：2005-09-27
申请号：US10734439
申请日：2003-12-11
申请人： Thomas Roehr , Michael Jacob
发明人： Thomas Roehr , Michael Jacob
CPC分类号： G11C11/22
摘要： A ferroelectric memory array includes a plurality of memory pages each formed of a plurality of ferroelectric memory cells. The ferroelectric memory cells are supplied by common word lines. Status memory cells are connected to each of the plurality of memory pages, each status memory cell stores the status of the memory page to which it is connected. A plurality of sense amplifiers each receives inputs from a pair of bit lines. Each of the bit lines receives inputs from the ferroelectric memory cells of a plurality of the memory pages. The sense amplifiers write back data into the memory cells and status cells in reversed states following read operations.
摘要翻译： 铁电存储器阵列包括由多个铁电存储器单元形成的多个存储器页。 铁电存储单元由公用字线提供。 状态存储器单元连接到多个存储器页中的每一个，每个状态存储单元存储与其连接的存储器页的状态。 多个读出放大器各自接收来自一对位线的输入。 每个位线接收来自多个存储器页的铁电存储单元的输入。 在读操作之后，感测放大器将数据写入存储单元和状态单元。
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