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    Method for determining a reliable oxide thickness
    3.
    发明授权
    Method for determining a reliable oxide thickness 失效
    确定可靠的氧化物厚度的方法

    公开(公告)号：US6133746A

    公开(公告)日：2000-10-17

    申请号：US163414

    申请日：1998-09-30

    申请人： Peng Fang ,  Hao Fang

    发明人： Peng Fang ,  Hao Fang

    IPC分类号： G01N27/92 ,  H01L23/544 ,  G01R31/12 ,  H01L21/66

    CPC分类号： H01L22/34 ,  G01N27/92

    摘要： A method for determining a reliable gate oxide thickness for a transistor involves subjecting test transistors to an alternating current (AC) voltage until the test transistors break down. The breakdown times of the test transistors are measured and correlated with the corresponding gate oxide thickness of the test transistor to form a reliability model of the transistor. The reliable gate oxide thickness is determined by extrapolating the reliability model out to a predetermined period of time for which reliability is desired, for example, ten years.

    摘要翻译： 用于确定晶体管的可靠栅极氧化物厚度的方法包括使测试晶体管经受交流（AC）电压，直到测试晶体管分解为止。 测量测试晶体管的击穿时间并与测试晶体管的相应栅极氧化物厚度相关联，以形成晶体管的可靠性模型。 可靠的栅极氧化物厚度通过将可靠性模型推断到需要可靠性的预定时间段（例如十年）来确定。

    Method and System for Providing Contact to a First Polysilicon Layer in a Flash Memory Device
    4.
    发明申请
    Method and System for Providing Contact to a First Polysilicon Layer in a Flash Memory Device 有权
    用于在闪存器件中提供与第一多晶硅层的接触的方法和系统

    公开(公告)号：US20120302017A1

    公开(公告)日：2012-11-29

    申请号：US13566741

    申请日：2012-08-03

    申请人： Mark S. CHANG ,  Hao Fang ,  King Wai Kelwin Ko

    发明人： Mark S. CHANG ,  Hao Fang ,  King Wai Kelwin Ko

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

    摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

    摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻穿过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。

    METHODS FOR ACTIVE BOOSTING TO MINIMIZE CAPACITIVE COUPLING EFFECT BETWEEN ADJACENT GATES OF FLASH MEMORY DEVICES
    6.
    发明申请
    METHODS FOR ACTIVE BOOSTING TO MINIMIZE CAPACITIVE COUPLING EFFECT BETWEEN ADJACENT GATES OF FLASH MEMORY DEVICES 有权
    用于主动加速以最小化闪存存储器件相邻栅极之间的电容耦合效应的方法

    公开(公告)号：US20080144384A1

    公开(公告)日：2008-06-19

    申请号：US12031640

    申请日：2008-02-14

    申请人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

    发明人： Tuan D. Pham ,  Masaaki Higashitani ,  Hao Fang ,  Gerrit Jan Hemink

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  H01L23/5222 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.

    摘要翻译： NAND闪存器件采用独特的增压板设计。 升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。 升压板还屏蔽浮动栅极之间的不必要的耦合。 自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。 因此，根据本发明可以实现更紧凑和可靠的存储器件。

    Over-writing data in a recording system
    7.
    发明授权
    Over-writing data in a recording system 有权
    在录音系统中重写数据

    公开(公告)号：US07167330B2

    公开(公告)日：2007-01-23

    申请号：US11100162

    申请日：2005-04-06

    申请人： Carl F. Elliott ,  Hao Fang ,  Ross S. Wilson

    发明人： Carl F. Elliott ,  Hao Fang ,  Ross S. Wilson

    IPC分类号： G11B5/03

    CPC分类号： G11B20/1403 ,  G11B5/012 ,  G11B20/00086 ,  G11B20/0021 ,  G11B20/00579 ,  G11B20/10009 ,  G11B20/10425 ,  G11B2020/10898 ,  G11B2220/2516

    摘要： A recording system stores recording cycle information identifying the parameters for recording user data on a particular data sector. During a subsequent operation, the recording system employs the recording cycle information to select a different set of parameters for recording new user data at the particular data sector. One of the parameters might identify a recorded pattern in a balance pad at the data sector, and another one of the parameters might identify a scrambler seed value. By employing a different set of recording parameters for each occurrence of recording user data at the particular sector, sample timing of, for example, a read channel might be based on an average of easy and hard transitions.

    摘要翻译： 记录系统存储识别用于在特定数据扇区上记录用户数据的参数的记录周期信息。 在随后的操作期间，记录系统采用记录周期信息来选择用于在特定数据扇区记录新用户数据的不同参数集合。 参数中的一个可以识别数据扇区中的平衡衬垫中的记录模式，另一个参数可以识别加扰器种子值。 通过对特定扇区的记录用户数据的每次出现采用不同的记录参数集合，例如读通道的采样定时可以基于简单和硬转换的平均值。

    Method of forming poly insulator poly capacitors by using a self-aligned salicide process
    8.
    发明授权
    Method of forming poly insulator poly capacitors by using a self-aligned salicide process 失效
    通过使用自对准自对准硅化物工艺形成多晶硅绝缘体聚电容器的方法

    公开(公告)号：US07141469B2

    公开(公告)日：2006-11-28

    申请号：US10967198

    申请日：2004-10-19

    申请人： Jung-Cheng Kao ,  Hao Fang

    发明人： Jung-Cheng Kao ,  Hao Fang

    IPC分类号： H01L21/8238

    CPC分类号： H01L28/60 ,  H01L27/0629

    摘要： A method of forming poly insulator poly capacitors by using self-aligned salicide process for mixed mode analog devices. These capacitors are formed in the self-aligned salicide process as stacked poly insulator poly (PIP) capacitors. In the self-aligned salicide process, a self-aligned salicide block process is needed to protect the the salicide formation process from electrostatic discharge (ESD) devices such as resistors or capacitors. The oxide layer of the self-aligned salicide block is used as the dielectric layer of the capacitors to form the PIP capacitor. Therefore, some process steps are omitted due to the formation of the PIP capacitors.

    摘要翻译： 通过对混合模式模拟装置使用自对准自对准硅化物工艺形成多晶硅绝缘体多晶硅电容器的方法。 这些电容器在自对准的自对准硅化物工艺中形成为堆叠的多晶硅绝缘体聚（PIP）电容器。 在自对准的自对准硅化物工艺中，需要自对准的自对准硅化物阻挡工艺来保护自对准硅化物形成工艺免受例如电阻器或电容器的静电放电（ESD）器件的影响。 自对准硅化物块的氧化物层用作电容器的电介质层以形成PIP电容器。 因此，由于形成PIP电容器，省略了一些处理步骤。

    Impedance-matched write circuit with shunted matching resistor
    9.
    发明申请
    Impedance-matched write circuit with shunted matching resistor 有权
    具有分流匹配电阻的阻抗匹配写电路

    公开(公告)号：US20050174668A1

    公开(公告)日：2005-08-11

    申请号：US10776701

    申请日：2004-02-11

    申请人： Hao Fang ,  Cameron Rabe

    发明人： Hao Fang ,  Cameron Rabe

    IPC分类号： G11B5/00 ,  G11B5/012 ,  G11B5/09

    CPC分类号： G11B5/012 ,  G11B2005/0013

    摘要： An impedance matched write circuit is provided that shunts one or more matching resistors. The impedance matched write circuit includes an interconnect for connecting to a write head and at least one resistor between a control voltage and the interconnect for impedance matching to the interconnect. A transistor can be connected across the resistor to shunt current that would otherwise pass through the resistor during an overshoot mode. The transistor may be a PMOS transistor or a combination of PMOS and NMOS transistors. A gate voltage of the transistor is controlled by a source such that the transistor is turned on in an overshoot mode and turned off during a steady state mode.

    摘要翻译： 提供阻抗匹配写电路，其分流一个或多个匹配电阻器。 阻抗匹配写入电路包括用于连接到写入头的互连和用于与互连的阻抗匹配的控制电压和互连之间的至少一个电阻器。 晶体管可以跨过电阻连接，以分流电流，否则在过冲模式下电流将通过电阻。 晶体管可以是PMOS晶体管或PMOS和NMOS晶体管的组合。 晶体管的栅极电压由源极控制，使得晶体管以过冲模式导通，并在稳态模式期间截止。

    Semiconductor device having reduced field oxide recess and method of fabrication
    10.
    发明授权
    Semiconductor device having reduced field oxide recess and method of fabrication 失效
    具有减小的场氧化物凹陷的半导体器件和制造方法

    公开(公告)号：US06492229B2

    公开(公告)日：2002-12-10

    申请号：US09729516

    申请日：2000-12-04

    申请人： Masaaki Higashitani ,  Toru Ishigaki ,  Hao Fang

    发明人： Masaaki Higashitani ,  Toru Ishigaki ,  Hao Fang

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： A semiconductor device having reduced field oxide recess and method of fabrication is disclosed. The method of fabricating the semiconductor device begins by performing an HF dip process on a substrate after field oxidation followed by performing a select gate oxidation. Thereafter, a core implant and a field implant are performed. After the implants, a tunnel oxide mask is deposited. The select gate oxide is then etched in areas uncovered by the tunnel oxide mask, and tunnel oxidation is performed.

    摘要翻译： 公开了一种具有减小的场氧化物凹陷和制造方法的半导体器件。 制造半导体器件的方法是通过在场氧化之后对衬底进行HF浸渍法，然后进行选择栅极氧化而开始的。 此后，进行核心植入和场植入。 在植入物之后，沉积隧道氧化物掩模。 然后在不被隧道氧化物掩模覆盖的区域中蚀刻选择栅极氧化物，并且执行隧道氧化。