公开(公告)号：US08283718B2

公开(公告)日：2012-10-09

申请号：US11611856

申请日：2006-12-16

申请人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

发明人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

摘要翻译： 提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层 该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

公开(公告)号：US07374654B1

公开(公告)日：2008-05-20

申请号：US10978845

申请日：2004-11-01

申请人： Mark S. Chang ,  Sergey D. Lopatin ,  Ramkumar Subramanian

发明人： Mark S. Chang ,  Sergey D. Lopatin ,  Ramkumar Subramanian

IPC分类号： C25F3/00 ,  C25F7/00 ,  C25D5/18 ,  C25D5/10 ,  B23H7/00

CPC分类号： C23C28/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/56 ,  H01L27/285

摘要： A method of making an organic memory cell which comprises two electrodes with a controllably conductive media between the two electrodes is disclosed. The present invention involves providing a dielectric layer having formed therein one or more first electrode pads; removing a portion of the first electrode pad to form a recessed area on top of the pads and in the dielectric layer using reverse electroplating; forming a controllably conductive media over the first electrode pad in the recessed area; and forming a second electrode over the conductive media. The controllably conductive media contains an organic semiconductor layer and a passive layer.

摘要翻译： 公开了一种制造有机存储单元的方法，该方法包括在两个电极之间具有可控导电介质的两个电极。 本发明涉及提供在其中形成有一个或多个第一电极焊盘的电介质层; 去除所述第一电极焊盘的一部分以在所述焊盘的顶部和所述电介质层中使用反向电镀形成凹陷区域; 在所述凹陷区域中的所述第一电极焊盘上形成可控导电介质; 以及在所述导电介质上形成第二电极。 可控导电介质包含有机半导体层和无源层。

公开(公告)号：US06979619B1

公开(公告)日：2005-12-27

申请号：US09941370

申请日：2001-08-28

申请人： Hao Fang ,  Yue-Song He ,  Mark S. Chang ,  Kent K. Chang

发明人： Hao Fang ,  Yue-Song He ,  Mark S. Chang ,  Kent K. Chang

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11543

摘要： In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area. Finally, a nitridation process is provided in both the core and periphery areas subsequent to the previous steps. In a second aspect of the present invention, a flash memory device is disclosed. The flash memory device comprises core area having a plurality of memory transistors comprising an oxide layer, a first poly layer, an interpoly dielectric layer, and a second poly layer. The flash memory device further comprises a periphery area having a plurality of transistors comprising an oxide layer, a portion of the first poly layer, and the second poly layer. According to the present invention, the method for fabricating the flash memory device is a simplified process that results in a significant improvement in the oxide reliability in the core and periphery areas and also eliminates the nitrogen contamination problem in the periphery area.

摘要翻译： 在本发明的第一方面中，公开了一种制造闪速存储器件的方法。 该方法包括以下步骤：在存储器件的外围区域中提供双栅极氧化物的一部分，然后在存储器件的核心区域中同时提供双栅极氧化物，并在周边区域中完成双栅极氧化物。 最后，在上述步骤之后，在核心区域和外围区域都提供氮化处理。 在本发明的第二方面，公开了一种闪速存储器件。 闪存器件包括具有包括氧化物层，第一多晶硅层，多晶硅间介电层和第二多晶硅层的多个存储晶体管的核心区域。 闪存器件还包括具有包括氧化物层，第一多晶硅层的一部分和第二多晶硅层的多个晶体管的外围区域。 根据本发明，用于制造闪速存储器件的方法是简化的工艺，其显着提高了芯部和外围区域中的氧化物可靠性，并且还消除了周边区域中的氮污染问题。

公开(公告)号：US06900488B1

公开(公告)日：2005-05-31

申请号：US10284946

申请日：2002-10-31

申请人： Sergey D. Lopatin ,  Mark S. Chang ,  Minh Van Ngo ,  Patrick K. Cheung

发明人： Sergey D. Lopatin ,  Mark S. Chang ,  Minh Van Ngo ,  Patrick K. Cheung

IPC分类号： H01L27/28 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40 ,  H01L29/76

CPC分类号： H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0021 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/0077 ,  H01L51/0078

摘要： The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of the lower electrode. An Inter Layer Dielectric (ILD) is formed above the passive layers and lower electrode, whereby a via or other type relief is created within the ILD and an organic semiconductor material is then utilized to partially fill the via above the passive layer. The portions of the via that are not filled with organic material are filled with dielectric material, thus forming a multi-dimensional memory structure above the passive layer or layers and the lower electrode. One or more top electrodes are then added above the memory structure, whereby distinctive memory cells are created within the organic portions of the memory structure and activated (e.g., read/write) between the top electrodes and bottom electrode, respectively. In this manner, multiple storage cells can be formed within a singular organic structure thereby increasing memory device density and storage.

摘要翻译： 本发明提供一种多小区有机存储装置，其可以作为具有构造在存储装置内的多个多小区结构的非易失性存储装置来操作。 可以形成下电极，其中在下电极的顶部上形成一个或多个钝化层。 在无源层和下电极之上形成层间电介质（ILD），由此在ILD内产生通孔或其它类型的浮雕，然后利用有机半导体材料部分地填充钝化层以上的通孔。 通孔中没有填充有机材料的部分用电介质材料填充，从而在钝化层或下层电极之上形成多维存储结构。 然后在存储器结构上方添加一个或多个顶部电极，由此在存储器结构的有机部分内分别创建独特的存储单元，并分别在顶部电极和底部电极之间激活（例如，读取/写入）。 以这种方式，可以在单个有机结构内形成多个存储单元，从而增加存储器件密度和存储。

公开(公告)号：US06815292B1

公开(公告)日：2004-11-09

申请号：US10260061

申请日：2002-09-27

申请人： Hao Fang ,  Mark S. Chang

发明人： Hao Fang ,  Mark S. Chang

IPC分类号： H01L2972

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531

摘要： A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

公开(公告)号：US06773954B1

公开(公告)日：2004-08-10

申请号：US10313494

申请日：2002-12-05

申请人： Ramkumar Subramanian ,  Jane V. Oglesby ,  Sergey D. Lopatin ,  Mark S. Chang ,  Christopher F. Lyons ,  James J. Xie ,  Minh Van Ngo

发明人： Ramkumar Subramanian ,  Jane V. Oglesby ,  Sergey D. Lopatin ,  Mark S. Chang ,  Christopher F. Lyons ,  James J. Xie ,  Minh Van Ngo

IPC分类号： H01L5140

CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L27/28 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0043 ,  H01L51/0053 ,  H01L51/0059 ,  H01L51/0062 ,  H01L51/0077 ,  H01L51/0078 ,  H01L51/0081 ,  H01L51/0085

摘要： Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.

摘要翻译： 公开了在两个电极之间制造由具有可控导电介质的两个电极制成的有机存储单元的方法。 可控导电介质包含有机半导体层和无源层。 特别地，描述了形成电极和相邻钝化层的新颖方法。

公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

公开(公告)号：US06638358B1

公开(公告)日：2003-10-28

申请号：US09483176

申请日：2000-01-13

申请人： Lu You ,  Mark S. Chang ,  Hao Fang

发明人： Lu You ,  Mark S. Chang ,  Hao Fang

IPC分类号： B05C500

CPC分类号： H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/316 ,  H01L21/823468

摘要： The present invention is a method and system for processing a semiconductor device, the semiconductor device comprising at least two gate stacks and a spacer gap. The method and system comprise utilizing a spin-on technique at the transistor device level to provide an oxide spacer in the spacer gap and then curing the semiconductor device at a temperature above approximately 450° C. Through the use of a system/method in accordance with the present invention, the voids that are created in the spacer gaps during conventional semiconductor processing are eliminated. Furthermore, the oxide spacers posses the high quality characteristics that are typically provided through the use of the conventional CVD methodology. Accordingly, as a result of the use of the system/method in accordance with the present invention, the MOSFET oxide spacers are strengthened, which increases the reliability of the semiconductor device.

摘要翻译： 本发明是用于处理半导体器件的方法和系统，该半导体器件包括至少两个栅极叠层和间隔物间隙。 该方法和系统包括利用晶体管器件级上的旋涂技术在间隔物间隙中提供氧化物隔离物，然后在高于约450℃的温度下固化半导体器件。通过使用根据本发明的系统/方法 利用本发明，消除了在常规半导体处理期间在间隔物间隙中产生的空隙。 此外，氧化物间隔物具有通常通过使用常规CVD方法提供的高质量特性。 因此，通过使用根据本发明的系统/方法的结果，MOSFET氧化物间隔物被加强，这增加了半导体器件的可靠性。

公开(公告)号：US06475847B1

公开(公告)日：2002-11-05

申请号：US10109526

申请日：2002-03-27

申请人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

发明人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/115 ,  H01L2924/3011

摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

摘要翻译： 公开了一种缩小半导体器件并最小化自动掺杂问题的方法。 蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。 衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷 电介质层自动掺入源和漏极。

公开(公告)号：US06445051B1

公开(公告)日：2002-09-03

申请号：US09563797

申请日：2000-05-02

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko ,  John Jianshi Wang ,  Michael K. Templeton ,  Lu You ,  Angela T. Hui

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/28273

摘要： A method and system for providing a plurality of contacts in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and a plurality of field insulating regions adjacent to a portion of the plurality of gate stacks. The method and system include providing an etch stop layer covering the plurality of field insulating regions. The etch stop layer has an etch selectivity different from a field insulating region etch selectivity of the plurality of field insulating regions. The method and system also include providing an insulating layer covering the plurality of gate stacks, the plurality of field insulating regions and the etch stop layer. The method and system further include etching the insulating layer to provide a plurality of contact holes. The insulating layer etching step uses the etch stop layer to ensure that the insulating etching step does not etch through the plurality of field insulating regions. The method and system also include filling the plurality of contact holes with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供多个触点的方法和系统。 闪存器件包括多个栅极堆叠和与多个栅极堆叠的一部分相邻的多个场绝缘区域。 该方法和系统包括提供覆盖多个场绝缘区域的蚀刻停止层。 蚀刻停止层具有与多个场绝缘区域的场绝缘区蚀刻选择性不同的蚀刻选择性。 该方法和系统还包括提供覆盖多个栅极叠层，多个场绝缘区域和蚀刻停止层的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供多个接触孔。 绝缘层蚀刻步骤使用蚀刻停止层来确保绝缘蚀刻步骤​​不会蚀刻穿过多个场绝缘区域。 该方法和系统还包括用导体填充多个接触孔。