公开(公告)号：US08114784B2

公开(公告)日：2012-02-14

申请号：US12904593

申请日：2010-10-14

申请人： Haowen Bu ,  Che-Jen Hu ,  Rajesh Khamankar

发明人： Haowen Bu ,  Che-Jen Hu ,  Rajesh Khamankar

IPC分类号： H01L21/31

CPC分类号： H01L21/3185 ,  C23C14/0652 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/7843

摘要： Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

摘要翻译： 集成电路（IC）通常含有具有压应力的预金属电介质（PMD）衬垫，以增加MOS晶体管中的电子和空穴迁移率。 该增加受到PMD衬套的厚度的限制。 本发明是集成电路中的多层PMD衬垫，其具有比单层PMD衬垫更高的应力。 将本发明的PMD衬垫中的每个层暴露于含氮等离子体，并且具有高于1300MPa的压缩应力。 本发明的PMD衬垫由3〜10层构成。 可以增加第一层的氢含量以改善诸如闪烁噪声和负偏压温度不稳定性（NBTI）的晶体管特性。 还要求一种包含本发明的PMD衬垫的IC及其形成方法。

公开(公告)号：US06627955B2

公开(公告)日：2003-09-30

申请号：US10043507

申请日：2002-01-14

申请人： Craig T. Salling ,  Zhiqiang Wu ,  Che-Jen Hu

发明人： Craig T. Salling ,  Zhiqiang Wu ,  Che-Jen Hu

IPC分类号： H01L2362

CPC分类号： H01L27/0277 ,  H01L21/26513 ,  H01L29/1079

摘要： Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

公开(公告)号：US07514309B2

公开(公告)日：2009-04-07

申请号：US11184337

申请日：2005-07-19

申请人： Seetharaman Sridhar ,  Craig Hall ,  Che-Jen Hu ,  Antonio Luis Pacheco Rotondaro

发明人： Seetharaman Sridhar ,  Craig Hall ,  Che-Jen Hu ,  Antonio Luis Pacheco Rotondaro

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.

摘要翻译： 制造具有保护衬垫和/或层的半导体器件。 阱区和隔离区形成在半导体本体内。 栅电介质层形成在半导体本体上。 在栅极电介质层上形成诸如多晶硅的栅电极层。 在栅电极层上形成保护栅衬。 形成限定栅极结构的抗蚀剂掩模。 图案化栅极电极层以形成栅极结构。 偏移间隔件形成在栅极结构的横向边缘上，然后在阱区域中形成延伸区域。 然后在门结构的侧边缘上形成侧壁间隔物。 形成覆盖器件的NMOS区域的NMOS保护区域层。 在PMOS区域内执行凹陷蚀刻，随后形成应变引发凹陷结构。

公开(公告)号：US06716695B1

公开(公告)日：2004-04-06

申请号：US10326188

申请日：2002-12-20

申请人： Sunil V. Hattangady ,  Jaideep Mavoori ,  Che-Jen Hu ,  Rajesh B. Khamankar

发明人： Sunil V. Hattangady ,  Jaideep Mavoori ,  Che-Jen Hu ,  Rajesh B. Khamankar

IPC分类号： H01L218242

CPC分类号： H01L29/518 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

公开(公告)号：US20070020839A1

公开(公告)日：2007-01-25

申请号：US11184337

申请日：2005-07-19

申请人： Seetharaman Sridhar ,  Craig Hall ,  Che-Jen Hu ,  Antonio Luis Rotondaro

发明人： Seetharaman Sridhar ,  Craig Hall ,  Che-Jen Hu ,  Antonio Luis Rotondaro

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.

摘要翻译： 制造具有保护衬垫和/或层的半导体器件。 阱区和隔离区形成在半导体本体内。 栅电介质层形成在半导体本体上。 在栅极电介质层上形成诸如多晶硅的栅电极层。 在栅电极层上形成保护栅衬。 形成限定栅极结构的抗蚀剂掩模。 图案化栅极电极层以形成栅极结构。 偏移间隔件形成在栅极结构的横向边缘上，然后在阱区域中形成延伸区域。 然后在门结构的侧边缘上形成侧壁间隔物。 形成覆盖器件的NMOS区域的NMOS保护区域层。 在PMOS区域内执行凹陷蚀刻，随后形成应变引发凹陷结构。

公开(公告)号：US06956267B2

公开(公告)日：2005-10-18

申请号：US10783081

申请日：2004-02-19

申请人： Sunil V. Hattangady ,  Jaideep Mavoori ,  Che-Jen Hu ,  Rajesh B. Khamankar

发明人： Sunil V. Hattangady ,  Jaideep Mavoori ,  Che-Jen Hu ,  Rajesh B. Khamankar

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/518 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

摘要翻译： 制造晶体管的方法包括提供具有表面的半导体衬底，并在衬底的表面之外形成氮化物层。 氮化物层被氧化以形成氮化层之下的包含氧化物层的氮化硅氧化物层。 高K层沉积在氮化物层外面，导电层形成在高K层的外侧。 对导电层，高K层和氮化硅氧化物层进行蚀刻和图案化以形成栅叠层。 侧壁间隔物形成在与栅叠层相邻的半导体衬底的外侧，并且源极/漏极区形成在邻近侧壁间隔物的半导体衬底中。

公开(公告)号：US06764909B2

公开(公告)日：2004-07-20

申请号：US10446760

申请日：2003-05-28

申请人： Craig T. Salling ,  Zhiqiang Wu ,  Che-Jen Hu

发明人： Craig T. Salling ,  Zhiqiang Wu ,  Che-Jen Hu

IPC分类号： H01L21336

CPC分类号： H01L27/0277 ,  H01L21/26513 ,  H01L29/1079

摘要： Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

摘要翻译： 横向MOS晶体管的结构和制造方法，其位于以第一导电类型的半导体制造的集成电路的表面上，包括源极和漏极，每个在源极和漏极处具有延伸到 中心定位的栅极，限定所述晶体管的有效面积; 以及在所述第一导电类型的所述半导体内的半导体区域，其电阻率高于半导体的其余部分，该区域在晶体管的垂直方向上延伸，同时横向限制于晶体管的面积，使得栅极下的电阻率不同于 源极和漏极区下的电阻率。

公开(公告)号：US06730556B2

公开(公告)日：2004-05-04

申请号：US10313357

申请日：2002-12-06

申请人： Zhiqiang Wu ,  Che-Jen Hu

发明人： Zhiqiang Wu ,  Che-Jen Hu

IPC分类号： H01L218238

CPC分类号： H01L21/823814 ,  H01L21/823864

摘要： An integrated circuit device (60) including a first transistor (PMOS) of a first conductivity type and a second transistor (NMOS) of a second conductivity type that is complementary to the first conductivity type. The method includes the steps of forming a first gate stack (100), the first transistor including the first gate stack and forming a second gate stack (80), the second transistor including the second gate stack. The method further includes implanting a first drain extension region (107) at a first distance relative to the first gate stack, the first transistor including the first drain extension region, and the method includes implanting a second drain extension region (87) at a second distance relative to the second gate stack, the second transistor including the second drain extension region. The first distance is greater than the second distance.

摘要翻译： 一种包括第一导电类型的第一晶体管（PMOS）和与第一导电类型互补的第二导电类型的第二晶体管（NMOS）的集成电路器件（60）。 该方法包括以下步骤：形成第一栅极堆叠（100），第一晶体管包括第一栅极堆叠并形成第二栅极堆叠（80），第二晶体管包括第二栅极堆叠。 该方法还包括相对于第一栅极堆叠以第一距离注入第一漏极延伸区域（107），第一晶体管包括第一漏极延伸区域，并且该方法包括在第二漏极延伸区域 相对于第二栅极堆叠的距离，第二晶体管包括第二漏极延伸区域。 第一距离大于第二距离。