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1.发明授权Variable voltage, variable impedance CMOS off-chip driver and receiver interface and circuits 失效可变电压，可变阻抗CMOS片外驱动器和接收器接口和电路
公开(公告)号：US6060905A
公开(公告)日：2000-05-09
申请号：US598084
申请日：1996-02-07
申请人： Harry Randall Bickford , Chin-An Chang , Paul William Coteus , Robert Heath Dennard , Daniel Mark Dreps , Gerard Vincent Kopcsay
发明人： Harry Randall Bickford , Chin-An Chang , Paul William Coteus , Robert Heath Dennard , Daniel Mark Dreps , Gerard Vincent Kopcsay
IPC分类号： H01L21/8238 , G11C11/407 , H01L27/092 , H03K19/00 , H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018585 , H03K19/0005
摘要： An electronic apparatus is disclosed having: a plurality of electronic devices with the same or different internal voltages; an interconnection between two or more of the plurality of electronic devices; each of said two or more electronic devices has an internal voltage; driver and receiver circuits which send and receive signals at a selectable communication voltage levels for interfacing between said two or more electronic devices, at a common communication voltage which is less than the highest value of said internal voltages of said two or more electronic devices; a circuit for configuring the driver and receiver circuits; and the driver circuit are configured to have a substantially constant output impedance independent of their output voltage.
摘要翻译： 公开了一种电子设备，其具有：具有相同或不同内部电压的多个电子设备; 所述多个电子设备中的两个或更多个之间的互连; 所述两个或更多个电子设备中的每一个具有内部电压; 驱动器和接收器电路，其以可选择的通信电压电平发送和接收信号，用于在所述两个或更多个电子设备的所述内部电压的最高值的公共通信电压下在所述两个或更多个电子设备之间进行接口; 用于配置驱动器和接收器电路的电路; 并且驱动器电路被配置为具有独立于其输出电压的基本上恒定的输出阻抗。
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公开(公告)号：US08604828B1
公开(公告)日：2013-12-10
申请号：US08657849
申请日：1996-05-31
申请人： Harry Randall Bickford , Paul William Coteus , Robert Heath Dennard , Daniel Mark Dreps , Gerard Vincent Kopcsay
发明人： Harry Randall Bickford , Paul William Coteus , Robert Heath Dennard , Daniel Mark Dreps , Gerard Vincent Kopcsay
IPC分类号： H03K19/0175
CPC分类号： H03K19/0005 , H03K19/018521 , H03K19/018585
摘要： A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.
摘要翻译： 描述了具有多个具有相同或不同的内部CMOS电压的电子器件的结构; 两个或多个电子设备之间的互连; 驱动器和接收器电路，其提供用于与几代CMOS技术接口的可选输入/输出电压电平，从而允许以这种技术制造的芯片使用最适合于每个芯片的信号电压范围进行通信; 用于选择或调整所使用的接收器电路的类型的电路，从而允许使用具有外部提供的参考电压的差分比较器电路，或者使用具有可调阈值的逆变器式接收器，该选择通过设置 外部参考预定电压; 用于选择或调整逆变器接收器电路的开关阈值的电路，其使得能够针对给定输入信号电压范围适当地设定阈值。
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公开(公告)号：US6098176A
公开(公告)日：2000-08-01
申请号：US16788
申请日：1998-01-30
申请人： Paul William Coteus , Daniel Mark Dreps , Frank Ferraiolo , Gerard Vincent Kopcsay , Todd Edward Takken
发明人： Paul William Coteus , Daniel Mark Dreps , Frank Ferraiolo , Gerard Vincent Kopcsay , Todd Edward Takken
CPC分类号： G06F1/10
摘要： A clock signal distribution system is disclosed for providing synchronous clock signals to a plurality of electronic circuit devices. The system includes a clock signal generator means for providing a single frequency sinusoidal clock signal output and a plurality of electronic circuit devices. A clock signal distribution network including interconnected resonant segments of a transmission line 13 connected to the clock signal of the clock signal generator and to the plurality of electronic circuit devices for providing separate synchronous, phase aligned clock signals to the electronic circuit devices. The transmission line segments have lengths matched to the clock signal frequency wavelengths to eliminate clock signal distribution problems such as skew, jitter and pulse distortions.
摘要翻译： 公开了一种用于向多个电子电路装置提供同步时钟信号的时钟信号分配系统。 该系统包括用于提供单频正弦时钟信号输出的时钟信号发生器装置和多个电子电路装置。 时钟信号分配网络，包括连接到时钟信号发生器的时钟信号的传输线路13的互连谐振段，以及多个电子电路装置，用于向电子电路装置提供单独的同步相位对准的时钟信号。 传输线段具有与时钟信号频率波长匹配的长度，以消除诸如偏斜，抖动和脉冲失真的时钟信号分配问题。
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公开(公告)号：US06292903B1
公开(公告)日：2001-09-18
申请号：US09106639
申请日：1998-06-29
IPC分类号： G06F104
CPC分类号： G06F13/1689
摘要： A method and apparatus are disclosed for initiating a start-up operation of a system (1′) having a master device (1) and a slave device (14a-14n). The method comprises steps of: A) exercising the slave device (14a-14n) using the master device (1) to determine a temporal range within which temporal relationships of electrical signals need to be set in order to operate the system (1′) without error; B) setting the temporal relationships of the electrical signals so as to be within the determined temporal range; and C) storing a record of the determined temporal range, for subsequent use in operating the system (1′). In one embodiment of the invention, the system (1′) includes a memory control system of a computer system (1″), and the slave device (14a-14n) includes memory devices of the computer system (1″). The method of the invention substantially compensates for any differences in times of arrival for data being transferred from the master device (1) to the slave device (14a-14n), and vice versa, and thus minimizes the possibility of read/write errors being encountered, while increasing the overall processing speed and efficiency of the system (1′).
摘要翻译： 公开了一种用于启动具有主设备（1）和从设备（14a-14n）的系统（1'）的启动操作的方法和装置。 该方法包括以下步骤：A）使用主设备（1）来执行从设备（14a-14n）以确定需要设置电信号的时间关系以便操作系统（1'）的时间范围， 没有错误; B）将电信号的时间关系设置在所确定的时间范围内; 和C）存储所确定的时间范围的记录，以供随后在操作系统（1'）中使用。 在本发明的一个实施例中，系统（1'）包括计算机系统（1“）的存储器控制系统，并且从设备（14a-14n）包括计算机系统（1”）的存储设备。 本发明的方法基本上补偿从主设备（1）传送到从设备（14a-14n）的数据的到达时间的任何差异，反之亦然，从而使读/写错误的可能性最小化 同时提高系统的整体处理速度和效率（1'）。
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公开(公告)号：US6127840A
公开(公告)日：2000-10-03
申请号：US42912
申请日：1998-03-17
IPC分类号： H03K5/007 , H03K19/0175 , H04L25/02 , H03K17/16 , H03K19/003
CPC分类号： H04L25/0278 , H04L25/028 , H04L25/0292
摘要： A first circuit and a second circuit are connected by a pumped signal line that conducts a signal having a plurality of states. A dynamic termination circuit is connected to the pumped signal line. The dynamic termination circuit includes a switch responsive to the signal conducted by the pumped signal line such that the dynamic termination circuit is enabled only in response to certain of the plurality of states of the signal. In one embodiment, the switch is a first transistor that is coupled in series with a first impedance between a first reference voltage and an intermediate node. In this embodiment, the dynamic termination circuit further includes a second transistor coupled in series with a second impedance between a second reference voltage and the intermediate node and only first and second inverters that are each coupled between the intermediate node and the control input of a respective one of the first transistor and the second transistor.
摘要翻译： 第一电路和第二电路通过导通具有多个状态的信号的泵浦信号线连接。 动态终端电路连接到泵浦信号线。 动态终端电路包括响应于由泵浦信号线传导的信号的开关，使得动态终端电路仅在响应于信号的多个状态中的某些状态时被使能。 在一个实施例中，开关是与第一参考电压和中间节点之间的第一阻抗串联耦合的第一晶体管。 在该实施例中，动态终端电路还包括与第二参考电压和中间节点之间的第二阻抗串联耦合的第二晶体管，并且仅包括第一和第二反相器，每个反相器耦合在相应的中间节点和控制输入端 第一晶体管和第二晶体管之一。
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6.发明申请Method for Performing Memory Diagnostics Using a Programmable Diagnostic Memory Module 失效使用可编程诊断内存模块执行内存诊断的方法公开(公告)号：US20090049341A1
公开(公告)日：2009-02-19
申请号：US11840498
申请日：2007-08-17
CPC分类号： G06F11/24
摘要： A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译： 使用可编程诊断存储器模块执行存储器诊断的方法提供了存储器控制器和存储器子系统设计的增强的可测试性。 可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。 改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度 存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。 存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。
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7.发明申请公开(公告)号：US20080175327A1
公开(公告)日：2008-07-24
申请号：US12058689
申请日：2008-03-29
IPC分类号： H04B3/00
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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公开(公告)号：US07362697B2
公开(公告)日：2008-04-22
申请号：US10339757
申请日：2003-01-09
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。
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9.发明授权Method and apparatus for supplying a reference voltage for chip-to-chip communication 有权用于提供用于芯片到芯片通信的参考电压的方法和装置公开(公告)号：US06891406B2
公开(公告)日：2005-05-10
申请号：US10339754
申请日：2003-01-09
CPC分类号： H04L25/06
摘要： A method for receiving data by an integrated circuitry chip includes receiving data signals and a first clock signal sent by a sending chip. The data signals are received by data receivers and the clock signal is received by at least one clock receiver of the receiving chip. A reference voltage is derived by reference voltage circuitry for the receiving chip responsive to the first clock signal. Logical states of the received data signals are detected. The detecting includes the data receivers comparing voltage levels of the received data signals to the derived reference voltage.
摘要翻译： 一种用于由集成电路芯片接收数据的方法包括接收由发送芯片发送的数据信号和第一时钟信号。 数据信号由数据接收器接收，时钟信号由接收芯片的至少一个时钟接收器接收。 参考电压由对应于第一时钟信号的接收芯片的参考电压电路导出。 检测出接收到的数据信号的逻辑状态。 该检测包括数据接收器，将接收的数据信号的电压电平与导出的参考电压进行比较。
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公开(公告)号：US06725304B2
公开(公告)日：2004-04-20
申请号：US09740248
申请日：2000-12-19
IPC分类号： G06F1342
CPC分类号： G06F13/4269
摘要： An apparatus for connecting circuit modules is disclosed. The apparatus for connecting circuit modules that receives an input and an output signal at one circuit module and uses a transmitter/receiver to transmit data to and receive data from the second circuit module. Each transmitter/receiver is selectable between a bidirectional mode that transmits and simultaneously receives via two transmission lines, and a unidirectional mode that transmits on a first transmission line and receives from a second transmission line.
摘要翻译： 公开了一种用于连接电路模块的装置。 用于连接在一个电路模块处接收输入和输出信号的电路模块的装置，并且使用发射机/接收机向第二电路模块发送数据和从第二电路模块接收数据。 每个发射机/接收机可以在通过两条传输线路发送和同时接收的双向模式之间进行选择;以及单向模式，其在第一传输线路上传输并从第二传输线路接收。
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