摘要:
A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.
摘要:
An electronic apparatus is disclosed having: a plurality of electronic devices with the same or different internal voltages; an interconnection between two or more of the plurality of electronic devices; each of said two or more electronic devices has an internal voltage; driver and receiver circuits which send and receive signals at a selectable communication voltage levels for interfacing between said two or more electronic devices, at a common communication voltage which is less than the highest value of said internal voltages of said two or more electronic devices; a circuit for configuring the driver and receiver circuits; and the driver circuit are configured to have a substantially constant output impedance independent of their output voltage.
摘要:
A clock signal distribution system is disclosed for providing synchronous clock signals to a plurality of electronic circuit devices. The system includes a clock signal generator means for providing a single frequency sinusoidal clock signal output and a plurality of electronic circuit devices. A clock signal distribution network including interconnected resonant segments of a transmission line 13 connected to the clock signal of the clock signal generator and to the plurality of electronic circuit devices for providing separate synchronous, phase aligned clock signals to the electronic circuit devices. The transmission line segments have lengths matched to the clock signal frequency wavelengths to eliminate clock signal distribution problems such as skew, jitter and pulse distortions.
摘要:
A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.
摘要:
A data capture technique for high speed signaling to allow for optimal sampling of an asynchronous data stream. This technique allows for extremely high data rates and does not require that a clock be sent with the data as is done in source synchronous systems. The present invention also provides a hardware mechanism for automatically adjusting transmission delays for optimal two-bit simultaneous bi-directional (SiBiDi) signaling.
摘要:
Methods and apparatus are provided for choosing an energy-efficient coolant temperature for electronics by considering the temperature dependence of the electronics' power dissipation. This dependence is explicitly considered in selecting the coolant temperature T0 that is sent to the equipment. To minimize power consumption PTotal for the entire system, where PTotal=P0+PCool is the sum of the electronic equipment's power consumption P0 plus the cooling equipment's power consumption PCool, PTotal is obtained experimentally, by measuring P0 and PCool, as a function of three parameters: coolant temperature T0; weather-related temperature T3 that affects the performance of free-cooling equipment; and computational state C of the electronic equipment, which affects the temperature dependence of its power consumption. This experiment provides, for each possible combination of T3 and C, the value T0* of T0 that minimizes PTotal. During operation, for any combination of T3 and C that occurs, the corresponding optimal coolant temperature T0* is selected, and the cooling equipment is commanded to produce it.
摘要:
Methods and apparatus are provided for choosing an energy-efficient coolant temperature for electronics by considering the temperature dependence of the electronics' power dissipation. This dependence is explicitly considered in selecting the coolant temperature T0 that is sent to the equipment. To minimize power consumption PTotal for the entire system, where PTotal=P0+PCool is the sum of the electronic equipment's power consumption P0 plus the cooling equipment's power consumption PCool, PTotal is obtained experimentally, by measuring P0 and PCool, as a function of three parameters: coolant temperature T0; weather-related temperature T3 that affects the performance of free-cooling equipment; and computational state C of the electronic equipment, which affects the temperature dependence of its power consumption. This experiment provides, for each possible combination of T3 and C, the value T*0 of T0 that minimizes PTotal. During operation, for any combination of T3 and C that occurs, the corresponding optimal coolant temperature T*0 is selected, and the cooling equipment is commanded to produce it.
摘要:
A method and system for reducing the computation complexity and improving accuracy of delay and crosstalk calculation in transmission-lines with frequency-dependent losses. An analysis tool based on restricted coupled-line topologies, simple two-dimensional to three-dimensional RLC matrix conversion, and use of prestored synthesized circuits that accurately capture frequency-dependent loss effects. The CAD tool can handle frequency-dependent resistive and inductive effects for coupled-interconnections on large microprocessor chips with >10K of critical nets. This is done in an interactive manner during the design cycle and allows first path fast product design.