公开(公告)号：US09595443B2

公开(公告)日：2017-03-14

申请号：US13277642

申请日：2011-10-20

申请人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

发明人： Ming Zhu ,  Hui-Wen Lin ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Yuan-Sheng Huang ,  Ryan Chia-Jen Chen ,  Chao-Cheng Chen ,  Kuo-Cheng Ching ,  Ting-Hua Hsieh ,  Carlos H. Diaz

IPC分类号： H01L21/70 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/42376 ,  H01L29/4966

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，包括围绕并分离P活性区域和N-有源区域的隔离区域; 在P-活性区域上的P金属栅电极，并且在隔离区域上延伸，其中P金属栅电极包括P功函数金属和P功函数金属与衬底之间的含氧TiN层; 以及N型金属栅电极，其在N-有源区上方并在隔离区上方延伸，其中N型金属栅电极包括N功函数金属和N功函数金属与衬底之间的富氮TiN层 其中富氮TiN层在隔离区域上连接到含氧TiN层。

公开(公告)号：US08664079B2

公开(公告)日：2014-03-04

申请号：US13316817

申请日：2011-12-12

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。

公开(公告)号：US08525270B2

公开(公告)日：2013-09-03

申请号：US12713395

申请日：2010-02-26

申请人： Lee-Wee Teo ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/70

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

摘要： The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

摘要翻译： 所描述的方法和结构用于防止接触金属（例如W）水平地突出到相邻设备的门堆叠中，以影响这些相邻设备的功能。 定义了与设备相邻并且共享（或连接到）金属栅极的接触插塞下面的金属栅，并且衬有具有良好阶梯覆盖的功函数层，以防止接触金属挤出到相邻器件的栅极堆叠中。 仅涉及用于去除伪多晶硅的光掩模的掩模布局的修改。 不需要额外的光刻操作或掩模。 因此，不涉及制造工艺或附加的基板处理步骤（或操作）的修改。 使用上述方法和结构的好处可以包括提高器件产量和性能。

公开(公告)号：US20120319180A1

公开(公告)日：2012-12-20

申请号：US13162453

申请日：2011-06-16

申请人： Harry-Hak-Lay Chuang ,  Ming Zhu

发明人： Harry-Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L21/823437 ,  H01L29/66181 ,  H01L29/94

摘要： An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a gate structure disposed over a substrate; a source region and a drain region disposed in the substrate, wherein the gate structure interposes the source region and the drain region; and at least one post feature embedded in the gate structure.

摘要翻译： 公开了一种集成电路器件及其制造方法。 在一个示例中，集成电路器件包括设置在衬底上的栅极结构; 设置在所述基板中的源极区域和漏极区域，其中所述栅极结构插入所述源极区域和所述漏极区域; 以及嵌入在门结构中的至少一个后置特征。

公开(公告)号：US08304840B2

公开(公告)日：2012-11-06

申请号：US12846261

申请日：2010-07-29

申请人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02 ,  H01L21/70 ,  H01L27/088

CPC分类号： H01L29/401 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088

摘要： The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.

摘要翻译： 本公开涉及半导体器件的间隔结构。 半导体器件的示例性结构包括具有第一有源区和第二有源区的衬底; 多个在所述第一有源区上具有栅间距的第一栅电极，其中每个第一栅电极具有第一宽度; 与所述多个第一栅电极相邻的多个第一间隔件，其中每个第一间隔件具有第三宽度; 多个第二栅电极，其具有与第二有源区上的多个第一栅电极相同的栅极间距，其中每个第二栅电极具有大于第一宽度的第二宽度; 以及与所述多个第二栅电极相邻的多个第二间隔件，其中每个第二间隔件具有小于所述第三宽度的第四宽度。

公开(公告)号：US08378428B2

公开(公告)日：2013-02-19

申请号：US12893338

申请日：2010-09-29

申请人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82385 ,  H01L29/66545

摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.

摘要翻译： 应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

公开(公告)号：US08349678B2

公开(公告)日：2013-01-08

申请号：US12701824

申请日：2010-02-08

申请人： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

发明人： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate.

摘要翻译： 制造横向扩散的金属氧化物半导体（LDMOS）晶体管的方法包括在衬底上形成虚拟栅极。 在虚拟栅极的相对侧上的衬底上形成源极和漏极。 在源上形成第一硅化物。 在漏极上形成第二硅化物，使得至少一个漏极或源极的非硅化区域与虚拟栅极相邻。 漏极的非硅化区域提供能够承受适合于高电压LDMOS应用的电压负载的电阻区域。 在虚拟栅极上执行替换栅极处理以形成栅极。

公开(公告)号：US08143137B2

公开(公告)日：2012-03-27

申请号：US12706782

申请日：2010-02-17

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。

公开(公告)号：US20110210403A1

公开(公告)日：2011-09-01

申请号：US12713395

申请日：2010-02-26

申请人： Lee-Wee TEO ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee TEO ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/768

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

摘要： The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

摘要翻译： 所描述的方法和结构用于防止接触金属（例如W）水平地突出到相邻设备的门堆叠中，以影响这些相邻设备的功能。 定义了与设备相邻并且共享（或连接到）金属栅极的接触插塞下面的金属栅，并且衬有具有良好阶梯覆盖的功函数层，以防止接触金属挤出到相邻器件的栅极堆叠中。 仅涉及用于去除伪多晶硅的光掩模的掩模布局的修改。 不需要额外的光刻操作或掩模。 因此，不涉及制造工艺或附加的基板处理步骤（或操作）的修改。 使用上述方法和结构的好处可以包括提高器件产量和性能。

公开(公告)号：US09142414B2

公开(公告)日：2015-09-22

申请号：US13331214

申请日：2011-12-20

申请人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

发明人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

摘要翻译： 一种方法包括形成PMOS器件。 该方法包括在半导体衬底和PMOS区域上形成栅极电介质层，在栅极电介质层和PMOS区域上形成第一含金属层，对PMOS区域中的第一含金属层进行处理 使用含氧处理气体，并在第一含金属层和PMOS区域上形成第二含金属层。 第二含金属层具有低于硅的中间间隙功函数的功函数。 第一含金属层和第二含金属层形成PMOS器件的栅极。