公开(公告)号：US4420055A

公开(公告)日：1983-12-13

申请号：US297349

申请日：1981-08-28

申请人： Hartmut Grutzediek ,  Joachim Scheerer ,  Erich Knothe ,  Franz-Josef Melcher

发明人： Hartmut Grutzediek ,  Joachim Scheerer ,  Erich Knothe ,  Franz-Josef Melcher

IPC分类号： G01G7/04 ,  G01G7/00

CPC分类号： G01G7/045

摘要： Apparatus for measuring weight and force has a load reception part arranged for deflection on a fixed part of a weighing and force-measuring system and includes a compensation coil arrangement situated in a constant magnetic field. At least one position sensor ascertains load-dependent deflections of the load reception part from a predetermined position and feeds a sensor signal to an electric regulator circuit. The regulator circuit regulates the current through the compensation coil arrangement so that the load reception part is returned to its predetermined position. The regulator circuit includes means which impart, alternately, positive and negative values, determined by the loading, to the current flowing through the compensation coil arrangement.

摘要翻译： 用于测量重量和力的装置具有负载接收部分，其布置用于在称重和力测量系统的固定部分上偏转，并且包括位于恒定磁场中的补偿线圈装置。 至少一个位置传感器从预定位置确定负载接收部分的负载相关偏转并将传感器信号馈送到电调节器电路。 调节器电路调节通过补偿线圈装置的电流，使得负载接收部分返回到其预定位置。 调节器电路包括交替地将通过负载确定的正值和负值赋予流过补偿线圈装置的电流的装置。

公开(公告)号：US07488638B2

公开(公告)日：2009-02-10

申请号：US11297561

申请日：2005-12-08

申请人： Hartmut Grutzediek ,  Joachim Scheerer

发明人： Hartmut Grutzediek ,  Joachim Scheerer

IPC分类号： H01L21/8238

CPC分类号： H01L29/0882 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/823493 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A method for fabricating integrable PMOSFET semiconductor structures in a P-doped substrate which are distinguished by a high dielectric strength is provided. In order to fabricate the PMOSFET semiconductor structure, a mask is applied to a semiconductor substrate for the definition of a window delimited by a peripheral edge. An N-doped well is thereupon produced in the P-doped semiconductor substrate by means of high-voltage ion implantation through the window delimited by the mask, the edge zone of said N-doped well reaching as far as the surface of the semiconductor substrate. The individual regions for the source, drain and bulk of the PMOSFET semiconductor structure are then produced in the P-doped inner zone enclosed by the well. The P-doped inner zone forms the drift zone of the PMOSFET structure. Since the drift zone has the weak basic doping of the substrate, the PMOSFET has a high dielectric strength.

摘要翻译： 提供了通过高介电强度来区分在P掺杂衬底中制造可积分PMOSFET半导体结构的方法。 为了制造PMOSFET半导体结构，将掩模施加到半导体衬底以定义由周边界定界的窗口。 在P掺杂半导体衬底中通过通过由掩模限定的窗口的高压离子注入在其上产生N掺杂阱，所述N掺杂阱的边缘区域到达半导体衬底的表面 。 然后在由阱包围的P掺杂的内部区域中产生用于PMOSFET半导体结构的源极，漏极和体的各个区域。 P掺杂的内区形成PMOSFET结构的漂移区。 由于漂移区具有衬底的弱碱性掺杂，PMOSFET具有高介电强度。

公开(公告)号：US07271070B1

公开(公告)日：2007-09-18

申请号：US09806224

申请日：1999-08-13

申请人： Hartmut Grutzediek ,  Joachim Scheerer

发明人： Hartmut Grutzediek ,  Joachim Scheerer

IPC分类号： H01L27/416

CPC分类号： H01L29/66272 ,  H01L21/8222 ,  H01L21/8226 ,  H01L27/0233 ,  H01L27/082

摘要： The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is delimited by a peripheral edge. An n-doped trough is then produced in the semiconductor substrate by means of ion implantation using an energy that is sufficient for ensuring that a p-doped inner area remains on the surface of the semiconductor substrate. The edge area of the n-doped trough extends as far as the surface of the semiconductor substrate. The other n-doped and/or p-doped areas that make up the structure of the transistor or logic gate are then inserted into the p-doped inner area of the semiconductor substrate. The inventive method is advantageous in that it no longer comprises expensive epitaxy and insulation processes. In an n-doped semiconductor substrate, all of the implanted ions are replaced by the complementary species; i.e. n is exchanged for p and vice versa.

摘要翻译： 本发明涉及使用p掺杂半导体衬底制造可积分半导体元件，特别是晶体管或逻辑门的方法。 首先，将掩模施加到半导体衬底以便限定由外围边缘限定的窗口。 然后通过使用足以确保p掺杂的内部区域保留在半导体衬底的表面上的能量的离子注入在半导体衬底中产生n掺杂槽。 n掺杂槽的边缘区域延伸到半导体衬底的表面。 构成晶体管或逻辑门的结构的其他n掺杂和/或p掺杂区域然后被插入到半导体衬底的p掺杂内部区域中。 本发明的方法的优点在于其不再包括昂贵的外延和绝缘工艺。 在n掺杂半导体衬底中，所有注入的离子被互补物质所取代; 即n被交换为p，反之亦然。

公开(公告)号：US20060121666A1

公开(公告)日：2006-06-08

申请号：US11297561

申请日：2005-12-08

申请人： Hartmut Grutzediek ,  Joachim Scheerer

发明人： Hartmut Grutzediek ,  Joachim Scheerer

IPC分类号： H01L21/8238

CPC分类号： H01L29/0882 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/823493 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A method for fabricating integrable PMOSFET semiconductor structures in a P-doped substrate which are distinguished by a high dielectric strength is provided. In order to fabricate the PMOSFET semiconductor structure, a mask is applied to a semiconductor substrate for the definition of a window delimited by a peripheral edge. An N-doped well is thereupon produced in the P-doped semiconductor substrate by means of high-voltage ion implantation through the window delimited by the mask, the edge zone of said N-doped well reaching as far as the surface of the semiconductor substrate. The individual regions for the source, drain and bulk of the PMOSFET semiconductor structure are then produced in the P-doped inner zone enclosed by the well. The P-doped inner zone forms the drift zone of the PMOSFET structure. Since the drift zone has the weak basic doping of the substrate, the PMOSFET has a high dielectric strength.

公开(公告)号：US5779425A

公开(公告)日：1998-07-14

申请号：US758355

申请日：1996-12-03

申请人： Hartmut Grutzediek ,  Joachim Scheerer

发明人： Hartmut Grutzediek ,  Joachim Scheerer

IPC分类号： B65G49/07 ,  F24F3/16 ,  H01L21/00 ,  H01L21/677

CPC分类号： H01L21/67294 ,  F24F3/161 ,  H01L21/67718 ,  H01L21/67769 ,  H01L21/67781 ,  Y10S414/137 ,  Y10S414/14 ,  Y10S414/141

摘要： A technique for handling discs, such as wafers for integrated circuits, which must be processed in ultra-clean rooms and which are transported to various workstations for processing. A horizontally extended rail has storage positions therealong where standard commercial carriers are positioned which contain vertically standing wafers. A lifting device can lift any carrier over neighboring carriers and moves it to a carrying basket located on an extension of the rail. The carrying basket is then turned by 90.degree. so that the vertical wafers lie horizontally. A tongue-shaped device can be moved under any of these wafers for removal thereof from the basket and subsequent transport to a workstation, and return.

摘要翻译： 用于处理诸如用于集成电路的晶片的盘的技术，其必须在超洁净室中处理并被运送到各种工作站进行处理。 水平延伸的轨道具有存储位置，其中标准商业载体被定位成包含垂直放置的晶片。 提升装置可以将任何载体提升到相邻的载体上并将其移动到位于轨道的延伸部上的携带篮。 然后将搬运篮转动90度，使垂直晶片水平放置。 舌形装置可以在这些晶片中的任何一个下方移动，以将其从篮子中取出并随后运输到工作站，并返回。

公开(公告)号：US5718552A

公开(公告)日：1998-02-17

申请号：US641274

申请日：1996-04-30

申请人： Hartmut Grutzediek ,  Joachim Scheerer

发明人： Hartmut Grutzediek ,  Joachim Scheerer

IPC分类号： B65G49/07 ,  F24F3/16 ,  H01L21/00 ,  H01L21/677

CPC分类号： H01L21/67294 ,  F24F3/161 ,  H01L21/67718 ,  H01L21/67769 ,  H01L21/67781 ,  Y10S414/137 ,  Y10S414/14 ,  Y10S414/141

摘要： A technique for handling discs, such as wafers for integrated circuits, which must be processed in ultra-clean rooms and which are transported to various workstations for processing. A horizontally extended rail has storage positions therealong where standard commercial carriers are positioned which contain vertically standing wafers. A lifting device can lift any carrier over neighboring carriers and moves it to a carrying basket located on an extension of the rail. The carrying basket is then turned by 90.degree. so that the vertical wafers lie horizontally. A tongue-shaped device can be moved under any of these wafers for removal thereof from the basket and subsequent transport to a workstation, and return.

公开(公告)号：US5066955A

公开(公告)日：1991-11-19

申请号：US544682

申请日：1990-06-27

申请人： Joachim Scheerer ,  Hartmut Grutzediek

发明人： Joachim Scheerer ,  Hartmut Grutzediek

IPC分类号： H03M1/06 ,  H03M1/52

CPC分类号： H03M1/0697 ,  H03M1/52

摘要： Integrating analog to digital converter operating according to a multiple ramp procedure and having a charge storage or charge summation circuit which continuously up-integrates an input signal and which by means of a following comparator, a logic circuit and reference currents or reference voltages, down-integrates during periodically recurrent time intervals, the instants being defined by an oscillator, a timebase counter and a bistable stage. The time between two successive such instants being called a submeasurement. At the imput of the charge storage or charge summation circuit used for the input signal or at one its other inputs, convergence accelerating signals are superimposed after every nth (n=1,2,3, . . . ) submeasurement to provide for strongly enhanced convergence range and for shorter convergence period, and these convergence accelerating signals having Taylor series expansions according to time in the time interval of a submeasurement which are first or higher order polynomials.

摘要翻译： 集成模数转换器，其根据多斜坡程序进行操作，并具有电荷存储或电荷相加电路，其对输入信号进行连续上调，并且通过下一个比较器，逻辑电路和参考电流或参考电压， 在周期性周期性时间间隔期间集成，时钟由振荡器，时基计数器和双稳态阶段定义。 两个连续的这种时刻之间的时间称为子测量。 在用于输入信号或其它输入端的电荷存储或电荷求和电路的输入端，会在每n（n = 1,2,3，...）个子测量之后叠加收敛加速信号，以提供强大的增强 收敛范围和较短收敛期，以及这些收敛加速信号，其具有根据作为第一或更高阶多项式的子测量的时间间隔中的时间的泰勒级数展开。

公开(公告)号：US20070273007A1

公开(公告)日：2007-11-29

申请号：US11547532

申请日：2005-03-24

申请人： Hartmut Grutzediek ,  Michael Rammensee ,  Joachim Scheerer

发明人： Hartmut Grutzediek ,  Michael Rammensee ,  Joachim Scheerer

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/66272 ,  H01L29/0615 ,  H01L29/0821 ,  H01L29/7322

摘要： The invention relates to NPN and PNP bipolar transistors and to a method for the production thereof, said transistors being characterised by a particularly high collector-emitter and collector-base blocking voltage. The blocking voltage is increased by a particular doping profile. An NPN bipolar transistor comprises a p-doped substrate (1), a trenched n-doped layer (3) forming the collector, a p-doped layer (7) which is arranged above the trenched n-doped layer and is made of a base and an n-doped layer which is arranged within the p-doped layer and forms an emitter of the transistor. A spatial charge area (RLZ 1) is formed between the p-doped layer and the trenched n-doped layer and a second spatial charge area (RLZ 2) is formed between the trenched n-doped layer and the p-doped substrate, which expands in the vertical direction on the collector when the transistor is operated with an increasing potential. The trenched n-doped layer comprises a doping profile in such a manner that when the transistor is operated with an increasing potential, the first and the second spatial charge area expand on the collector, transversing the entire depth of the trenched n-doped layer prior to the critical field strength for a breakthrough being reached between the collector and emitter.

摘要翻译： 本发明涉及NPN和PNP双极晶体管及其制造方法，所述晶体管的特征在于特别高的集电极 - 发射极和集电极 - 基极阻断电压。 阻塞电压通过特定的掺杂分布增加。 NPN双极晶体管包括p掺杂衬底（1），形成集电极的沟槽n掺杂层（3），p掺杂层（7），其布置在沟槽n掺杂层上方并由 基极和n掺杂层，其被布置在p掺杂层内并形成晶体管的发射极。 在p掺杂层和沟槽n掺杂层之间形成空间电荷区域（RLZ 1），并且在沟槽n掺杂层和p掺杂衬底之间形成第二空间电荷区域（RLZ 2），其中 当晶体管以增加的电位运行时，在集电极上垂直方向扩展。 沟槽n掺杂层包括掺杂分布，使得当晶体管以增加的电势工作时，第一和第二空间电荷区在集电极上膨胀，横跨了沟槽n掺杂层的整个深度，之前 到集电极和发射极之间达到突破的临界场强。

公开(公告)号：US6021785A

公开(公告)日：2000-02-08

申请号：US899665

申请日：1997-07-24

申请人： Hartmut Grutzediek ,  Joachim Scheerer

发明人： Hartmut Grutzediek ,  Joachim Scheerer

IPC分类号： B08B3/12 ,  H01L21/00 ,  H01L21/306 ,  B08B6/00 ,  B08B3/00

CPC分类号： H01L21/02052 ,  B08B1/007 ,  B08B3/12 ,  H01L21/67051 ,  Y10S134/902

摘要： Procedure and device for cleaning disk-shaped objects, in particular wafers, with sonification and water as rinsing medium and coupling liquid between the ultrasonic transmitter and the surface which is to be cleaned, whereby the wafer is preferentially held by vacuum suction on a rotating plate and the radiating surface of an ultrasonic transmitter is approached to the surface which is to be cleaned to within a distance in the millimeter range and a flowing film of ultra-pure water is produced between the disk surface and the radiating transmitter surface. The particles dislodged from the disk surface by the sonification are carried away by the flowing water and ejected radially with the water by rotating the disk. The ejected water impinges on the sidewalls of a trough and is drained away without splashing. The size difference of the ultrasonic transmitter surface and the disk surface which is to be cleaned is compensated for by the relative motion between the ultrasonic transmitter and the disk, whereby the entire surface area of the disk is successively scanned by the ultrasonic transmitter.

摘要翻译： 用于以超声处理和水作为漂洗介质清洗盘形物体，特别是晶片的过程和装置，并且在超声波发射器和要被清洁的表面之间耦合液体，由此优选地通过真空抽吸将晶片保持在旋转板上 将超声波发射器的辐射表面接近要被清洁的表面到毫米范围内的距离内，并且在盘表面和辐射发射器表面之间产生超纯水的流动膜。 通过超声处理从盘表面移出的颗粒被流动的水带走，并通过旋转盘而与水径向喷射。 喷射的水撞击在槽的侧壁上，并且在没有飞溅的情况下被排出。 要通过超声波发射器和盘之间的相对运动来补偿超声波发射器表面和待清洁的盘表面的尺寸差异，由此通过超声波发射器连续地扫描盘的整个表面区域。

公开(公告)号：US5327137A

公开(公告)日：1994-07-05

申请号：US45576

申请日：1993-04-09

申请人： Joachim Scheerer ,  Hartmut Grutzediek

发明人： Joachim Scheerer ,  Hartmut Grutzediek

IPC分类号： H03M1/50

CPC分类号： H03M1/50

摘要： An analog-to-digital converter operates according to the multiple ramp procedure with continuous integration of the input signal in a charge storage or charge summation circuit, whereby downward integration is performed at periodically recurrent time intervals with the aid of a comparator circuit at the output of the charge storage or charge summation circuit, a logic circuit, a clock oscillator, a switching circuit, a first reference signal and a second reference signal. Hereby the duration of the switched-on state of one of the reference signals is a measure for the input signal. The transfer function of the quantization noise H.sub.q (z) with an n-th order (n=1,2,3, . . . ) high pass filter characteristic can be derived from a transfer function H(z) describing the specified configuration.

摘要翻译： 模数转换器根据多个斜坡程序操作，其中输入信号在电荷存储或电荷求和电路中连续积分，由此借助于输出端的比较器电路以周期性的周期性时间间隔进行向下积分 的电荷存储或电荷求和电路，逻辑电路，时钟振荡器，开关电路，第一参考信号和第二参考信号。 因此，参考信号之一的接通状态的持续时间是输入信号的量度。 可以从描述指定配置的传递函数H（z）导出具有n阶（n = 1,2,3，...）高通滤波器特性的量化噪声Hq（z）的传递函数。