公开(公告)号：US07326651B2

公开(公告)日：2008-02-05

申请号：US10905068

申请日：2004-12-14

申请人： Heidi Baks ,  Richard A. Bruff ,  Richard A. Conti ,  Allan Upham

发明人： Heidi Baks ,  Richard A. Bruff ,  Richard A. Conti ,  Allan Upham

IPC分类号： H01L21/302

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76804

摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

摘要翻译： 本发明涉及集成电路器件中的双镶嵌互连结构的制造。 具体地，公开了一种利用平面化材料和压缩扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。 阻挡材料优选具有大于300MPa的压缩应力。 在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。 然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。 在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。 然后可以将所得的双镶嵌结构金属化。 通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

公开(公告)号：US20050079701A1

公开(公告)日：2005-04-14

申请号：US10905068

申请日：2004-12-14

申请人： Heidi Baks ,  Richard Bruff ,  Richard Conti ,  Allan Upham

发明人： Heidi Baks ,  Richard Bruff ,  Richard Conti ,  Allan Upham

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76804

摘要： This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized. With this method, the problem of photoresist poisoning by the interlevel dielectric material is alleviated.

摘要翻译： 本发明涉及集成电路器件中的双镶嵌互连结构的制造。 具体地，公开了一种利用平面化材料和压缩扩散阻挡材料在低k电介质薄膜中形成单一或双镶嵌结构的方法。 阻挡材料优选具有大于300MPa的压缩应力。 在该方法的优选双镶嵌实施例中，首先在电介质材料中形成通孔，然后将平坦化材料沉积在通孔和介电材料上，并且阻挡材料沉积在平坦化材料上。 然后在成像材料中光刻地形成沟槽，通过阻挡材料蚀刻成平坦化材料，并将沟槽图案转移到电介质材料。 在这些蚀刻步骤期间和之后，去除成像，阻挡层和平坦化材料。 然后可以将所得的双镶嵌结构金属化。 通过这种方法，可以减轻层间电介质材料的光致抗蚀剂中毒问题。

公开(公告)号：US20070155186A1

公开(公告)日：2007-07-05

申请号：US11164419

申请日：2005-11-22

申请人： Heidi Baks ,  James Kelliher ,  Huang Liu

发明人： Heidi Baks ,  James Kelliher ,  Huang Liu

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02362 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02167 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A back-end-of-line (BEOL) interconnect structure and a method of forming an interconnect structure. The interconnect structure comprises a conductor, such as copper, embedded in a dielectric layer, and a low-k dielectric capping layer, which acts as a diffusion barrier, on the conductor. A method of forming the BEOL interconnect structure is disclosed, where the capping layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) and is comprised of Si, C, H, and N. The interconnect structure provides improved oxygen diffusion resistance and improved barrier qualities allowing for a reduction in film thickness.

摘要翻译： 后端行（BEOL）互连结构和形成互连结构的方法。 互连结构包括在导体上作为扩散阻挡层的埋入电介质层的导体（例如铜）和用作扩散阻挡层的低k电介质封盖层。 公开了形成BEOL互连结构的方法，其中使用等离子体增强化学气相沉积（PECVD）沉积覆盖层并且由Si，C，H和N组成。互连结构提供改善的耐氧扩散性和改进的 屏障质量允许减少膜厚度。

公开(公告)号：US20090176367A1

公开(公告)日：2009-07-09

申请号：US11970748

申请日：2008-01-08

申请人： Heidi Baks ,  James T. Kelliher ,  Huang Liu

发明人： Heidi Baks ,  James T. Kelliher ,  Huang Liu

IPC分类号： H01L21/768

CPC分类号： H01L21/02304 ,  H01L21/312 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A back-end-of-line (BEOL) interconnect structure and a method of forming an interconnect structure. The interconnect structure comprises a conductor, such as copper, embedded in a dielectric layer, and a low-k dielectric capping layer, which acts as a diffusion barrier, on the conductor. A method of forming the BEOL interconnect structure is disclosed, where the capping layer is deposited using plasma-enhanced chemical vapor deposition (PECVD) and is comprised of Si, C, H, and N. The interconnect structure provides improved oxygen diffusion resistance and improved barrier qualities allowing for a reduction in film thickness.

摘要翻译： 后端行（BEOL）互连结构和形成互连结构的方法。 互连结构包括在导体上作为扩散阻挡层的埋入电介质层的导体（例如铜）和用作扩散阻挡层的低k电介质封盖层。 公开了形成BEOL互连结构的方法，其中使用等离子体增强化学气相沉积（PECVD）沉积覆盖层并且由Si，C，H和N组成。互连结构提供改善的耐氧扩散性和改进的 屏障质量允许减少膜厚度。

公开(公告)号：US20070148966A1

公开(公告)日：2007-06-28

申请号：US11315923

申请日：2005-12-22

申请人： Heidi Baks ,  Shyng-Tsong Chen ,  Timothy Dalton ,  Nicholas Fuller ,  Kaushik Kumar

发明人： Heidi Baks ,  Shyng-Tsong Chen ,  Timothy Dalton ,  Nicholas Fuller ,  Kaushik Kumar

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76811

摘要： A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.

摘要翻译： 在有机硅酸盐玻璃层中形成镶嵌互连结构而不会损坏有机硅酸盐玻璃材料的方法。 该方法包括在有机硅酸盐玻璃层上形成硬掩模层堆叠，使用等离子体蚀刻和等离子体光致抗蚀剂去除方法的组合在硬掩模和有机硅酸盐玻璃层中限定开口，并执行一个或多个额外的等离子体蚀刻工艺 不包括含氧物质，以将开口蚀刻到形成镶嵌互连结构所需的深度，并除去由等离子体蚀刻和等离子体光致抗蚀剂去除工艺的组合损坏的任何有机硅酸盐材料。