公开(公告)号：US06787801B2

公开(公告)日：2004-09-07

申请号：US10247574

申请日：2002-09-19

Applicant: Helmut Fischer ,  Alan Morgan

Inventor： Helmut Fischer ,  Alan Morgan

IPC: H01L2358

CPC classification number: H01L22/32 ,  G01R31/2884 ,  G11C29/006 ,  G11C29/48 ,  G11C2029/1206

Abstract: Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.

Abstract translation: 通过经由至少一个连接线与相关联的集成电路电连接的附加电路部件在晶片级上测试集成电路。 附加电路部分集成在晶片的集成电路之间的间隙中。 集成电路的功能可以通过连接线控制。 例如，在诸如DRAM的存储器模块的情况下，集成电路的内部电压和/或电流即使在内部线路上也可以有利地被测量，否则这些线路将难以进入。 在将晶圆级测试和集成电路切割成单个芯片之后，附加电路部分变得不可用。

公开(公告)号：US06788228B2

公开(公告)日：2004-09-07

申请号：US10364014

申请日：2003-02-10

Applicant: Alan Morgan ,  Helmut Fischer

Inventor： Alan Morgan ,  Helmut Fischer

IPC: H03M700

CPC classification number: G11C29/781 ,  G11C29/787 ,  G11C29/812

Abstract: An addressing device selects an element from a set of N≦2K regular elements or alternatively from a set of R

Abstract translation: 寻址装置从一组N <= 2KK个常规元素中选择一个元素，或者根据一个R-N个冗余元素来选择一个元素，这取决于一个K位输入地址， N解码器，并且其解析常规元素。 对于每个冗余元件，提供旁路电路，并且在每种情况下都具有用于提供通过选择性破坏可编程的K个参考位或者通过选择性地引入导电链路以将比较器件设置为所选择的标识的参考位发射器 地址。 如果相关地址被识别，则旁路电路解决分配给它的冗余元件，同时关闭1-out-N解码器，只要它是敏感的。 对于其敏化，每个双稳态电路检查参考位的M

公开(公告)号：US09083951B2

公开(公告)日：2015-07-14

申请号：US13250518

申请日：2011-09-30

Applicant: Eben Upton ,  Graham Veitch ,  Alan Morgan ,  James Bennett

Inventor： Eben Upton ,  Graham Veitch ,  Alan Morgan ,  James Bennett

IPC: H04N7/12 ,  H04N19/42 ,  H04N19/127 ,  H04N19/156 ,  H04N19/187 ,  G06F15/16 ,  G06F13/364

CPC classification number: H04N19/182 ,  G06F13/364 ,  G06F15/16 ,  H04N19/127 ,  H04N19/156 ,  H04N19/187 ,  H04N19/439 ,  Y02D10/14

Abstract: Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.

Abstract translation: 为适应性强的视频架构提供了各种方法和系统。 在一个实施例中，用于调整视频设备的视频处理的方法包括沿着由多个互连的流水线元件限定的第一流水线路径处理视频流。 响应于检测到视频设备的系统状况的变化，通过重新配置管道元件互连中的至少一个，管线路径被转换到第二管道路径。 在另一个实施例中，一种方法包括获得视频流。 在视频设备的视频流水线中处理具有第一分辨率的第一子集比特流，并且在处理期间从视频流水线中提取视频信息。 所提取的视频信息的至少一部分然后到视频设备的视频流水线，用于处理具有高于第一分辨率的第二分辨率的第二子集比特流。

公开(公告)号：US06744682B2

公开(公告)日：2004-06-01

申请号：US10153766

申请日：2002-05-22

Applicant: Alan Morgan

Inventor： Alan Morgan

IPC: G11C2900

CPC classification number: G11C29/812

Abstract: A semiconductor memory apparatus includes a first and second memory bank. Each of these memory banks has a plurality of row and column lines and at least one redundant column line. An activation device selectively activates the redundant column line, thereby causing the redundant column line to become a replacement line for a defective column line. The activation device includes a plurality of programmable addressing fuses, and a programmable selection fuse having at least two electrical selection fuse states. The programmable selection fuse is configured such that an addressing fuse in the first selection fuse state is electrically associated with the first memory bank and an addressing fuse in the second selection fuse state is electrically associated with the second memory bank.

Abstract translation: 半导体存储装置包括第一和第二存储体。 这些存储体中的每一个具有多个行和列线以及至少一个冗余列线。 激活装置选择性地激活冗余列线，从而使冗余列线成为缺陷列线的替代线。 激活装置包括多个可编程寻址熔丝以及具有至少两个电选择熔丝状态的可编程选择熔丝。 可编程选择保险丝被配置为使得第一选择保险丝状态中的寻址熔丝与第一存储体电连接，并且第二选择保险丝状态中的寻址熔丝与第二存储体电连接。

公开(公告)号：US20160209544A1

公开(公告)日：2016-07-21

申请号：US14632677

申请日：2015-02-26

Applicant: Daniel A. Minguez ,  Thomas Matthew Laroche ,  Keith R. Thomas ,  Alan Morgan ,  Elizabeth Anna Edwards Johnson

Inventor： Daniel A. Minguez ,  Thomas Matthew Laroche ,  Keith R. Thomas ,  Alan Morgan ,  Elizabeth Anna Edwards Johnson

IPC: G01V99/00

CPC classification number: G01V99/005 ,  G01V1/282 ,  G01V11/00

Abstract: A method for quantitatively evaluating multiple computer-based plate tectonic models for application in a geographic region of interest, in some embodiments, comprises: selecting a plurality of computer-based plate tectonic models; using multiple computer-based plate tectonic models to generate one or more predictions for one or more geological parameters;obtaining observational data for each of said one or more geological parameters; for each of said one or more geological parameters, quantitatively comparing the predictions and the observational data to determine model rankings; and displaying said model rankings on a computer display.

Abstract translation: 在一些实施例中，一种用于定量评估在感兴趣的地理区域中应用的多个基于计算机的板块构造模型的方法包括：选择多个基于计算机的板块构造模型; 使用多个基于计算机的板块构造模型来生成一个或多个地质参数的一个或多个预测; 获取所述一个或多个地质参数中的每一个的观测数据; 对于所述一个或多个地质参数中的每一个，定量地比较预测和观测数据以确定模型排名; 并在计算机显示器上显示所述模型排名。

公开(公告)号：US20070062593A1

公开(公告)日：2007-03-22

申请号：US11228642

申请日：2005-09-17

Applicant: Andrew Morgan ,  Alan Morgan

Inventor： Andrew Morgan ,  Alan Morgan

IPC: B01F5/04

CPC classification number: B01F5/0413 ,  B01F5/0498 ,  B01F15/0429 ,  Y10T137/87627

Abstract: The specific application initially contemplated for the V-RAD invention is that of feed rate control of liquid chemical solutions for the purpose of municipal and industrial water treatment. In this application, a vacuum solution feed system is commonly operated by water forced through a Venturi nozzle to create a vacuum that is used to draw the liquid chemical solution into the water. In the prior art, feed rate control has been achieved by employing a variable area orifice control valve. However, in the application of liquid chemical solution injection for industrial and municipal water treatment, the variable area orifice concept has proven to be severely limited in its ability to provide stable and accurate feed rate control. The V-RAD invention provides a new and unique method of feed rate control designed to replace the variable area orifice concept and to provide a stable and accurate method of feed rate control.

Abstract translation: V-RAD发明初步设想的具体应用是用于市政和工业水处理的液体化学溶液的进料速率控制。 在该应用中，真空溶液进料系统通常通过文丘里喷嘴压力的水来运行，以产生用于将液体化学溶液吸入水中的真空。 在现有技术中，通过采用可变面积孔口控制阀来实现进给速度控制。 然而，在用于工业和城市水处理的液体化学溶液注入的应用中，可变面积孔概念已被证明在其提供稳定和准确的进料速率控制的能力方面受到严格限制。 V-RAD发明提供了一种新的独特的进给速率控制方法，旨在替代可变面积孔的概念，并提供稳定准确的进给速率控制方法。

公开(公告)号：US07162663B2

公开(公告)日：2007-01-09

申请号：US10676588

申请日：2003-10-01

Applicant: Peter Beer ,  Alan Morgan

Inventor： Peter Beer ,  Alan Morgan

IPC: G06F11/00

CPC classification number: G11C29/26 ,  G11C2029/2602 ,  G11C2029/3602

Abstract: A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Abstract translation: 并行测试第一和第二存储器电路。 可以根据电路选择信号来激活存储器电路，并且可以向第一和第二存储器电路施加控制信号。 控制信号根据第一或第二存储器电路的激活而启动相应的存储器电路中的功能。 在测试存储器电路时，将电路选择信号施加到第一存储器电路，并将反相电路选择信号施加到第二存储器电路，使得该功能根据电路在第一或第二存储器电路中启动 选择信号。

公开(公告)号：US20130022101A1

公开(公告)日：2013-01-24

申请号：US13250518

申请日：2011-09-30

Applicant: Eben Upton ,  Graham Veitch ,  Alan Morgan ,  James Bennett

Inventor： Eben Upton ,  Graham Veitch ,  Alan Morgan ,  James Bennett

IPC: H04N7/26

CPC classification number: H04N19/182 ,  G06F13/364 ,  G06F15/16 ,  H04N19/127 ,  H04N19/156 ,  H04N19/187 ,  H04N19/439 ,  Y02D10/14

Abstract: Various methods and systems are provided for adaptable video architectures. In one embodiment, a method for adapting video processing of a video device includes processing a video stream along a first pipeline pathway defined by a plurality of interconnected pipeline elements. In response to detecting a change in a system condition of the video device, the pipeline pathway is transitioned to a second pipeline pathway by reconfiguring at least one of the pipeline element interconnections. In another embodiment, a method includes obtaining a video stream. A first subset bitstream having a first resolution is processed in a video pipeline of a video device and video information is extracted from the video pipeline during the processing. At least a portion of the extracted video information is then to a video pipeline of the video device for processing a second subset bitstream having a second resolution higher than the first resolution.

Abstract translation: 为适应性强的视频架构提供了各种方法和系统。 在一个实施例中，用于调整视频设备的视频处理的方法包括沿着由多个互连的流水线元件限定的第一流水线路径处理视频流。 响应于检测到视频设备的系统状况的变化，通过重新配置管道元件互连中的至少一个，流水线路径被转换到第二管道路径。 在另一个实施例中，一种方法包括获得视频流。 在视频设备的视频流水线中处理具有第一分辨率的第一子集比特流，并且在处理期间从视频流水线中提取视频信息。 所提取的视频信息的至少一部分然后到视频设备的视频流水线，用于处理具有高于第一分辨率的第二分辨率的第二子集比特流。

公开(公告)号：US20120056377A1

公开(公告)日：2012-03-08

申请号：US12876934

申请日：2010-09-07

Applicant: Alan Morgan

Inventor： Alan Morgan

IPC: A63F9/00

CPC classification number: A63F3/0423 ,  A63F2003/0428

Abstract: The present invention relates to a crossword puzzle game. The game includes a medium. The game includes indicia displayed on the medium and representing a crossword portion having a plurality of adjacent cells for filling in intersecting words. The crossword portion has at least one clue for supplying at least one of the words. The game includes indicia displayed on the medium and representing a graphical puzzle portion the solution to which supplies another of the words, whereby solving the graphical puzzle portion promotes solving the crossword portion and, alternatively, solving the crossword portion promotes solving the graphical puzzle portion.

Abstract translation: 本发明涉及一种纵横字谜游戏。 游戏包括一个媒介。 游戏包括在介质上显示的标记，并且表示具有多个相邻单元格的填字游戏部分，用于填充相交字。 纵横字谜部分至少有一条提供至少一个字的线索。 游戏包括在媒体上显示的标记，并且表示提供另一个词的解决方案的图形拼图部分，由此解决图形拼图部分促进解决纵横字谜部分，或者，解决纵横字谜部分促进解决图形拼图部分。

公开(公告)号：US07219286B2

公开(公告)日：2007-05-15

申请号：US10154476

申请日：2002-05-22

Applicant: Alan Morgan

Inventor： Alan Morgan

IPC: G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2884 ,  G11C29/006 ,  G11C29/12 ,  G11C29/48 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A semiconductor device includes an integrated main circuit and an auxiliary circuit on a semiconductor substrate. The auxiliary circuit is configured to output and/or for receive electrical signals to and/or from the main circuit and is arranged at a distance from the main circuit in a kerf region of the semiconductor device. The main and auxiliary circuits each include a contact device that can be externally contact-connected to produce a temporary electrical signal connection between the main and auxiliary circuits.

Abstract translation: 半导体器件包括在半导体衬底上的集成主电路和辅助电路。 辅助电路被配置为输出和/或接收来自主电路的电信号和/或从主电路接收电信号，并且被布置在与半导体器件的切口区域中的主电路一定距离处。 主电路和辅助电路各自包括可以在外部接触连接以在主电路和辅助电路之间产生临时电信号连接的接触装置。