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    Method for fabricating a field effect-controlled semiconductor component
    1.
    发明授权
    Method for fabricating a field effect-controlled semiconductor component 失效
    用于制造场效应控制半导体部件的方法

    公开(公告)号：US06248620B1

    公开(公告)日：2001-06-19

    申请号：US09491095

    申请日：2000-01-24

    申请人： Helmut Strack ,  Helmut Gassel ,  Joost Larik

    发明人： Helmut Strack ,  Helmut Gassel ,  Joost Larik

    IPC分类号： H01L218238

    CPC分类号： H01L29/7802 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42376

    摘要： A method for fabricating field effect-controlled semiconductor components, such as e.g. but not exclusively MIS power transistors. The field effect-controllable semiconductor component has a semiconductor substrate of a first conductivity type and a gate insulator layer on the surface of the semiconductor substrate. A well of a second conductivity type is produced in the semiconductor substrate by implanting first impurity atoms. A semiconductor layer having a first predetermined thickness is produced on the gate insulator layer prior to the production of the well. The semiconductor layer is reduced in a predtdermined region to obtain a residual layer having a second predetermined thickness, such that the semiconductor layer acts as an implantation barrier outside the predetermined region when the well is produced.

    摘要翻译： 一种用于制造场效应控制半导体部件的方法，例如， 但不是唯一的MIS功率晶体管。 场效应可控半导体元件在半导体衬底的表面上具有第一导电类型的半导体衬底和栅极绝缘体层。 通过注入第一杂质原子在半导体衬底中产生第二导电类型的阱。 在生产井之前，在栅极绝缘体层上产生具有第一预定厚度的半导体层。 半导体层在预制区域中被还原以获得具有第二预定厚度的残余层，使得当制造阱时，半导体层用作预定区域外的注入势垒。

    Semiconductor Arrangement
    2.
    发明申请
    Semiconductor Arrangement 有权
    半导体安排

    公开(公告)号：US20070178624A1

    公开(公告)日：2007-08-02

    申请号：US11733930

    申请日：2007-04-11

    申请人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

    发明人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

    IPC分类号： H01L21/00 ,  H01L21/4763

    CPC分类号： H01L23/3192 ,  H01L24/05 ,  H01L25/16 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

    摘要： The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

    摘要翻译： 本发明涉及通过至少一个钝化层彼此电绝缘的至少两个半导体部件的垂直布置。 本发明同样涉及制造这种半导体装置的方法。 规定了一种半导体装置，其中特别地，例如由热机械载荷引起的金属化边缘处的开裂风险降低，制造规定的高含量的自由基氢被最小化。 此外，规定了制造这种半导体装置的方法。

    Semiconductor arrangement
    3.
    发明授权
    Semiconductor arrangement 有权
    半导体安排

    公开(公告)号：US07498194B2

    公开(公告)日：2009-03-03

    申请号：US11733930

    申请日：2007-04-11

    申请人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

    发明人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

    IPC分类号： H01L21/44

    CPC分类号： H01L23/3192 ,  H01L24/05 ,  H01L25/16 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

    摘要： The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

    摘要翻译： 本发明涉及通过至少一个钝化层彼此电绝缘的至少两个半导体部件的垂直布置。 本发明同样涉及制造这种半导体装置的方法。 规定了一种半导体装置，其中特别地，例如由热机械载荷引起的金属化边缘处的开裂风险降低，制造规定的高含量的自由基氢被最小化。 此外，规定了制造这种半导体装置的方法。

    Semiconductor arrangement
    6.
    发明申请
    Semiconductor arrangement 有权
    半导体安排

    公开(公告)号：US20050012215A1

    公开(公告)日：2005-01-20

    申请号：US10850157

    申请日：2004-05-20

    申请人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

    发明人： Nikolaus Bott ,  Oliver Haeberlen ,  Manfred Kotek ,  Joost Larik ,  Josef Maerz ,  Ralf Otremba

    IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/495

    CPC分类号： H01L23/3192 ,  H01L24/05 ,  H01L25/16 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

    摘要： The invention relates to a vertical arrangement of at least two semiconductor components which are electrically insulated from one another by at least one passivation layer. The invention likewise relates to a method for fabricating such a semiconductor arrangement. A semiconductor arrangement is specified in which, inter alia, the risk of cracking at the metallization edges, for example, caused by thermomechanical loading, is reduced and the fabrication-dictated high content of radical hydrogen is minimized. Furthermore, a method for fabricating such a semiconductor arrangement is specified.

    摘要翻译： 本发明涉及通过至少一个钝化层彼此电绝缘的至少两个半导体部件的垂直布置。 本发明同样涉及制造这种半导体装置的方法。 规定了一种半导体装置，其中特别地，例如由热机械载荷引起的金属化边缘处的开裂风险降低，并且制造规定的高含量的自由基氢被最小化。 此外，规定了制造这种半导体装置的方法。

    Circuit configuration for protecting an electronic circuit against overload
    9.
    发明授权
    Circuit configuration for protecting an electronic circuit against overload 失效
    用于保护电子电路免受过载的电路配置

    公开(公告)号：US5027181A

    公开(公告)日：1991-06-25

    申请号：US535367

    申请日：1990-06-08

    申请人： Joost Larik ,  Walter Forder

    发明人： Joost Larik ,  Walter Forder

    IPC分类号： H02H9/04

    CPC分类号： H02H9/042 ,  H02H9/041

    摘要： A circuit configuration for protecting electronic circuits against overload of a supply voltage source includes a voltage-limiting configuration, such as a Zener diode. A depletion layer field effect transistor is connected upstream of the voltage-limiting configuration and has interconnected gate and source terminals.

    摘要翻译： 用于保护电子电路免受电源电压源过载的电路配置包括电压限制配置，例如齐纳二极管。 耗尽层场效应晶体管连接在电压限制配置的上游，并具有互连的栅极和源极端子。